Analysis and implementation of a novel leading zero anticipation algorithm for floating-point arithmetic units

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 8, 2007, Pages 685-689

  Pappalardo, Francesco ^b   Visalli, Giuseppe ^b  

^a SAPIENZA UNIVERSITY OF ROME   (Italy)

^b STMicroelectronic   (Italy)

Author keywords

CMOS VLSI floating point unit (FPU); floating point arithmetic; leading zero anticipation (LZA)

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ERROR CORRECTION; IMAGE PROCESSING; VLSI CIRCUITS;

LEADING ZERO ANTICIPATION; MULTIMEDIA-ORIENTED SYSTEMS-ON-CHIPS;

DIGITAL ARITHMETIC;

EID: 34547899190     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.896937     Document Type: Article

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