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Volumn , Issue , 2013, Pages

In pursuit of instant gratification for FPGA design

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; TOOLS;

EID: 84898652778     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2013.6645505     Document Type: Conference Paper
Times cited : (14)

References (28)
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  • 9
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    • Jun
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  • 13
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    • Hermes: Lut fgpa technology mapping algorithm for area minimization with optimum depth
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    • Replace: An incremental placement algorithm for field programmable gate arrays
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    • (2009) FPL2009 , pp. 154-161
    • Leong, D.1    Lemieux, G.G.F.2
  • 16
    • 0031636125 scopus 로고    scopus 로고
    • Incremental routing in fpgas
    • J.M. Emmert and D. Bhatia, "Incremental routing in FPGAs," ASIC 1998, pp. 217-221, 1998.
    • (1998) ASIC 1998 , pp. 217-221
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    • HMFlow: Accelerated fpga compilation with hard macros for rapid prototyping
    • May
    • C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, B. Hutchings, "HMFlow: Accelerated FPGA Compilation with Hard Macros for Rapid Prototyping," FCCM 11, pp. 117-124, May 2011.
    • (2011) FCCM 11 , pp. 117-124
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    • Xilinx
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    • R. Soni, N. Steiner, M. French, "Open-Source Bitstream Generation", FCCM 13, pp. TBD, April 2013.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.