Incremental placement for layout-driven optimizations on FPGAs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 752-757

  Singh, Deshanand P ^a   Brown, Stephen D ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

INCREMENTAL PLACEMENT; LOGIC ELEMENTS;

ALGORITHMS; COMPUTER AIDED DESIGN; INTERCONNECTION NETWORKS; LOGIC DEVICES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036917243     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774683     Document Type: Conference Paper

References (7)

1. Altera. Altera 2000 Databook.
2. V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1999.
3. C. E. Cheng. RISA: Accurate and Efficient Placement Routability Modeling. In ICCAD 1994, pages 690-695, November 1994.
4. L. McMurchie and C. Ebeling, PathFinder: A negotiation-based performance-driven router for FPGAs, 1995.
5. S. Singh and S. Brown. Integrated Retiming and Placement for Field Programmable Gate Arrays. FPGA 2002.
6. D. Singh. Ph.D. Thesis, University of Toronto.
7. Xilinx. Xilinx 2000 Databook.