Replace: An incremental placement algorithm for field programmable gate arrays

FPL 09: 19th International Conference on Field Programmable Logic and Applications

Volumn , Issue , 2009, Pages 154-161

  Leong, David ^a   Lemieux, Guy G F ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN HIERARCHY; FLOOR-PLANNING; FLOORPLANS; INCREMENTAL PLACEMENT; INCREMENTAL PLACEMENT ALGORITHM; LARGE CIRCUITS; LARGE REGIONS; LOW TEMPERATURES; QUALITY DEGRADATION; RECOMPILING; REFINEMENT PROCESS; RUNTIMES; SUB-CIRCUITS; TIME-CONSUMING PROCESS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

ALGORITHMS;

EID: 70449922666     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2009.5272520     Document Type: Conference Paper

References (16)

1. D. Leong, "Incremental Placement for Field-Programmable Gate Arrays," M.A.Sc. Thesis, Dept of ECE, University of British Columbia, Nov., 2006.
2. V. Betz, 1. Rose, S. Marquardt Architecture and CAD for Deep-Submicron FPGAs, Kluwer, Feb., 1999.
3. C. Choy, T. Cheung, K. Wong, "Incremental Layout Placement Modification Algorithms," Trans. CAD, pp. 437445, Apr 1996.
4. Cong, M. Sarrafzadeh, "Incremental Physical Design," International Symposium on Physical Design, pp. 84-92, 2000.
5. J. Li, J. Yu, H. Miyashita, "An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree Representation," IEICE Trans. Fundamentals, vol. E88-A, no. 12, pp 3398-3404, 2005.
6. Z. Li, W. Wu, X. Hong, 1. Gu, "Incremental Placement Algorithm for Standard Cell Layout," IEEE ISCAS, vol.2 pp. 883-886, 2002.
7. A. Marquardt, V. Betz, J. Rose, "Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density," FPGA, pp. 37-46, 1999.
8. A. Singh and M. Marek-Sadowska, "Efficient Circuit Clustering for Area and Power Reduction in FPGAs," FPGA, 2002.
9. D. Singh, S. Brown, "Incremental Placement for Layout Driven Optimizations on FPGAs," ICCAD, pp. 752-759, 2002.
10. P. Suaris, L. Liu et al, "Incremental Physical Resynthesis for Timing Optimization," FPGA, pp. 99-108,2004.
11. N. Togawa, K. Hagi, M. Yanagisawa, "An Incremental Placement and Global Routing Algorithm for Field Programmable Gate Arrays," ASP-DAC, 1998.
12. M. Tom, D. Leong, G. Lemieux, "Un/DoPack: Re-Clustering of Large System-an-Chip Designs with Interconnect Variation for Low-Cost FPGAs", ICCAD, 2006.
13. D. Grant, G. Lemieux, "Perturb+Mutate: Semi-Synthetic Circuit Generation Incremental Placement and Routing", ACM TRETS, Sept. 2008.
14. H. Ren, D. Pan, C. Alpert, P. Villarrubia, "Diffusion-based Placement Migration," DAC, pp. 515-520, 2005.
15. M. Hrkic, J. Lillis, G. Beraudo, "An Approach to PlacementCoupled Logic Replication," DAC, pp. 711-716,2004.
16. S. Dutt, H. Ren, F. Yuan, V. Suthar, "A Network-flow Approach to Timing-driven Incremental Placement for ASICs," ICCAD, 2006.