Limitations of incremental signal-tracing for FPGA debug

Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

Volumn , Issue , 2012, Pages 49-56

  Hung, Eddie ^a   Wilton, Steven J E ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL WIDTHS; CIRCUIT DELAYS; DESIGN VERIFICATION; FLEXIBLE PLATFORMS; ON CHIPS; ROUTABILITY; RUNTIMES; SOFTWARE SIMULATION;

COMPUTER SOFTWARE; DESIGN; OBSERVABILITY; VERIFICATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84870706522     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2012.6339240     Document Type: Conference Paper

References (19)

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