A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 322-323

  Pilo, Harold ^a   Adams, Chad A ^a   Arsovski, Igor ^a   Houle, Robert M ^a   Lamphier, Steven M ^a   Lee, Michael M ^a   Pavlik, Frank M ^a   Sambatur, Sushma N ^b   Seferagic, Adnan ^a   Wu, Richard ^a   Younus, Mohammad I ^a  

^a IBM   (United States)

^b IBM INDIA RESEARCH LAB   (India)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE POWER; LEAKAGE REDUCTION; MEMORY BLOCKS; MEMORY DENSITY; POWER GATINGS; SOI TECHNOLOGY; SRAM LEAKAGE; SUPPLY VOLTAGES;

LEAKAGE CURRENTS;

STATIC RANDOM ACCESS STORAGE;

EID: 84876525376     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487753     Document Type: Conference Paper

References (5)

1. Narasimha, S., et al., "22nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL", IEDM, Dec. 2012
2. Barth, J., et al., "A 45nm SOI Embedded DRAM macro for POWER7TM 32MB On-Chip L3 Cache", ISSCC, pp. 342-343, Feb. 2010
3. Pilo, H., et al., "A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management," ISSCC, pp. 378-379, Feb. 2008
4. Hamzaoglu, F., et al., "A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-K Metal-Gate CMOS Technology", ISSCC, pp. 376-3779, Feb. 2008
5. Pilo, H., et al., "A 64Mb SRAM in 32nm High-k Metal-Gate SOI Technology with 0.7V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements," ISSCC, pp. 254-255, Feb. 2011