A 20nm 112Mb SRAM in High-κ metal-gate with assist circuitry for low-leakage and low-VMIN applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 316-317

  Chang, Jonathan ^a   Chen, Yen Huei ^a   Cheng, Hank ^a   Chan, Wei Min ^a   Liao, Hung Jen ^a   Li, Quincy ^a   Chang, Stanley ^a   Natarajan, Sreedhar ^a   Lee, Robin ^a   Wang, Ping Wei ^a   Lin, Shyue Shyh ^a   Wu, Chung Cheng ^a   Cheng, Kuan Lun ^a   Cao, Min ^a   Chang, George H ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY CONFIGURATIONS; CONVENTIONAL TECHNIQUES; HIGH PERFORMANCE APPLICATIONS; MOBILE APPLICATIONS; OPERATING VOLTAGE; PERFORMANCE DEGRADATION; SRAM CELL STABILITY; STATIC NOISE MARGIN;

CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS;

STATIC RANDOM ACCESS STORAGE;

EID: 84876563555     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487750     Document Type: Conference Paper

References (4)

1. K. Nii, et al, "A 45-nm Single-port and Dual port SRAM family with Robust Read/Write Stabilizing Circuitry under DVFS Environment", Dig. Symp. VLSI Circuits, Jun. 2008, pp. 212-213
2. K. Takeda et al, "Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs" Dig. Symp. VLSI Circuits, Jun. 2010, pp. 101-102
3. Y. Wang, et al, "Dynamic Behavior of SRAM Data Retention and a Novel Transient Voltage Collapse Technique for 0.6V 32nm LP SRAM", IEDM Digest of Technical Papers, 2011, pp. 741-744
4. Eric Karl, et al, "A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology with Integrated Active VMIN-Enhancing Assist Circuitry", ISSCC Digest of Technical Papers, Feb. 2012, pp 230-231