A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-Κ metal-gate CMOS with integrated power management

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 456-458

  Wang, Y ^a   Bhattacharya, U ^a   Hamzaoglu, F ^a   Kolar, P ^a   Ng, Y ^a   Wei, L ^a   Zhang, Y ^a   Zhang, K ^a   Bohr, M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349299081     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977505     Document Type: Conference Paper

References (5)

1. nd-Generation High-k + Metal- Gate Transistors, Enhanced Channel Strain and 0.171μmu; m2 SRAM Cell Size in a 291Mb Array, " IEDM Dig. Tech Papers, Dec. 2008.
2. F. Hamzaoglu, K. Zhang, Y. Wang, et al., "A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-κ Metel-Gate CMOS Technology, " ISSCC Dig. Tech. Papers, pp. 376-377, Feb. 2008.
3. E. Seevinck, F. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells, " IEEE J. Solid-State Circuits, vol.22, no.10, pp. 748-754, Oct. 1987.
4. M. Khellah et al, "Effect of Power Supply Noise on SRAM Dynamic Stability, " Symp. VLSI Circuit Dig., pp. 76-77, Jun. 2007
5. K. Kuhn, "Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability and Nanoscale CMOS, " IEDM Dig. Tech. Papers, pp. 471- 474, Dec. 2007.