A 64Mb SRAM in 32nm high-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 254-255

  Pilo, Harold ^a   Arsovski, Igor ^a   Batson, Kevin ^a   Braceras, Geordie ^a   Gabric, John ^a   Houle, Robert ^a   Lamphier, Steve ^a   Pavlik, Frank ^a   Seferagic, Adnan ^a   Chen, Liang Yu ^a   Ko, Shang Bin ^a   Radens, Carl ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

REFRACTORY METAL COMPOUNDS;

AGGRESSIVE SCALING; ASSIST FEATURES; CORNER ROUNDING; EQUIVALENT OXIDE THICKNESS; GATE ELECTRODES; HIGH-K METAL GATES; SIZE REDUCTIONS; SOI TECHNOLOGY;

DELAY CIRCUITS;

EID: 79955723758     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746307     Document Type: Conference Paper

References (5)

1. 2 SRAM and Ultra Low-k Back End with Eleven Levels of Copper," Symposium on VLSI Technology, June 2009.
2. Pilo, H., et al., "A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management," ISSCC Digest of Technical Papers, pp. 378-379, Feb. 2008.
3. Bhavnagarwala, A., et al., "A Sub-600mV, Fluctuation Tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing," Symposium on VLSI Circuits, pp. 78-79, June 2007.
4. 2 Cell in 32nm High-k Metal-Gate CMOS," ISSCC Digest of Technical Papers, pp. 348-349, Feb. 2010.
5. Kolar, P., et al., "A 32nm High-k Metal Gate SRAM with Adaptive Dynamic Stability Enhancement for Low-Voltage Operation," ISSCC Digest of Technical Papers, pp. 346-347, Feb. 2010.