Investigation of gross die per wafer formulas

IEEE Transactions on Semiconductor Manufacturing

Volumn 18, Issue 1, 2005, Pages 136-139

  De Vries, Dirk K ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Gross die per wafer (GDW); Potential good die; Yield

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; PARAMETER ESTIMATION;

GROSS DIE PER WAFER (GDW); POTENTIAL GOOD DIE; WAFER FABRICATIONS; YIELDS;

SEMICONDUCTOR MATERIALS;

EID: 13844256345     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2004.836656     Document Type: Article

References (6)

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3. G. D. Croft, R. L. Lomenick, D. L. Youngblood, and J. M. Johnston, "Die counting algorithm for yield modeling and die per wafer optimization," in Proc. SPIE, vol. 3216, 1997, pp. 186-196.
4. Semiconductor Technology Handbook, Technology Associates, Portola Valley, CA, 1993. O. D. Trapp, L. J. Lopp, R. A. Blanchard.
5. N. N. Muijen, "Philips Central TEO Tech. Note ER8191,", May 1968.
6. W. J. J. Rey, "How many chips per wafer? Derivation of the number of potential good dice per wafer," Philips Nat. Lab. Rep. 6230, Jun. 1995.