Coupling noise analysis for VLSI and ULSI circuits

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2000-January, Issue , 2000, Pages 485-489

  Aingaran, Kathirgamar ^a   Klass, Fabian ^a   Kim, Chin Man ^a   Amir, Chaim ^a   Mitra, Joydeep ^a   You, Eileen ^a   Mohd, Jamil ^a   Dong, Sai Keung ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; DIGITAL CIRCUITS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; MOSFET DEVICES; SENSITIVITY ANALYSIS; THRESHOLD VOLTAGE; ULSI CIRCUITS;

AGGRESSIVE SCALING; CAPACITIVE COUPLING NOISE; DEEP SUB-MICRON; DESIGN DATABASE; HIERARCHICAL APPROACH; MODERN HIGH PERFORMANCE; SUBSTRATE NOISE; SUPPLY VOLTAGES;

VLSI CIRCUITS;

EID: 4143058188     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838930     Document Type: Conference Paper

References (13)

1. T. Horel, G. Lauterbach, "UltraSPARC-III: designing third-generation 64-bit performance", IEEE MICRO, pp. 73-85, May/June 1999
2. W. Lynch, G. Lauterbach, "UltraSPARC-III: A 600 MHz 64-bit superscalar processor for 100-way scalable systems", HotChips Symposium, Stanford University, CA, August 1998.
3. K. Shepard, "Design Methodologies for Noise in Digital Integrated Circuits", Design Automation Conference, San Francisco CA, June 1998
4. A. Conn, et al, "Noise Considerations in Circuit Optimization", International Conference on Computer Aided Design, November 1998.
5. P. Gross, et al, "Determination of Worst-Case Aggressor Alignment for Delay Calculation", International Conference on Computer Aided Design, November 1998.
6. K. Shepard, V. Narayanan, "Noise in deep sub-micron digital design", International Conference on Computer Aided Design, November 1996.
7. S. Nakagawa, et al, "On-Chip Cross Talk Noise Model for Deep-Submicrometer ULSI Interconnect", Hewlett-Packard Journal, August 1998.
8. A. Rubio, et al, "An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 13, March 1994.
9. W. Chen, et al, "Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs", International Test Conference, November 1997.
10. J. Qian, et al, "Modeling the Effective Capacitance for the RC Interconnect of CMOS Gates", IEEE Transactions on Computer Aided Design on Integrated Circuits and Systems, vol. 13, December 1994.
11. L. Pileggi, "Coping with RC (L) Interconnect Induced Headaches", International Conference on Computer Aided Design, November 1995.
12. M. Shoji, "CMOS Digital Circuit Technology", Prentice-Hall, 1988, pp392-408.
13. W. Dally, J. Poulton, "Digital Systems Engineering", Cambride University Press, 1998, pp 260-298.