메뉴 건너뛰기




Volumn , Issue , 2013, Pages 630-637

Optimization of interconnects between accelerators and shared memories in dark silicon

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATOR DATA; COMPUTING PLATFORM; INTERCONNECT DESIGN; MEMORY-SHARING; ORDERS-OF-MAGNITUDE; PROBABILITY ANALYSIS; SHARED RESOURCES; SIGNAL ROUTING;

EID: 84893430012     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2013.6691182     Document Type: Conference Paper
Times cited : (17)

References (21)
  • 1
    • 77955114639 scopus 로고    scopus 로고
    • Introduction to the wire-speed processor and architecture
    • Jan.
    • H. Franke et al, "Introduction to the wire-speed processor and architecture", IBM Journal of Research and Development, vol. 54, no. 1, pp. 3:1-3:11, Jan. 2010.
    • (2010) IBM Journal of Research and Development , vol.54 , Issue.1 , pp. 31-311
    • Franke, H.1
  • 2
    • 49249086142 scopus 로고    scopus 로고
    • Larrabee: A many-core x86 architecture for visual computing
    • Aug.
    • L. Seiler et al, "Larrabee: A Many-Core x86 Architecture for Visual Computing", ACM Transactions on Graphics, vol. 27, no. 3, p. 1, Aug. 2008.
    • (2008) ACM Transactions on Graphics , vol.27 , Issue.3 , pp. 1
    • Seiler, L.1
  • 4
    • 51549087415 scopus 로고    scopus 로고
    • Run-time instruction set selection in a transmutable embedded processor
    • L. Bauer, M. Shafique, and J. Henkel, "Run-Time Instruction Set Selection in a Transmutable Embedded Processor", in Design Automation Conference (DAC), 2008, pp. 56-61.
    • (2008) Design Automation Conference (DAC) , pp. 56-61
    • Bauer, L.1    Shafique, M.2    Henkel, J.3
  • 5
    • 84863543742 scopus 로고    scopus 로고
    • Architecture Support for Accelerator-Rich CMPs
    • J. Cong et al., "Architecture Support for Accelerator-Rich CMPs", in Design Automation Conference, 2012, pp. 843-849.
    • (2012) Design Automation Conference , pp. 843-849
    • Cong, J.1
  • 6
    • 0345382713 scopus 로고    scopus 로고
    • Domain-specific codesign for embedded security
    • Apr.
    • P. Schaumont and I. Verbauwhede, "Domain-specific codesign for embedded security", Computer, vol. 36, no. 4, pp. 68-74, Apr. 2003.
    • (2003) Computer , vol.36 , Issue.4 , pp. 68-74
    • Schaumont, P.1    Verbauwhede, I.2
  • 7
    • 77954995378 scopus 로고    scopus 로고
    • Understanding sources of inefficiency in general-purpose chips
    • R. Hameed et al., "Understanding sources of inefficiency in general-purpose chips", International Symposium on Computer Architecture, p. 37, 2010.
    • (2010) International Symposium on Computer Architecture , pp. 37
    • Hameed, R.1
  • 8
    • 84863550559 scopus 로고    scopus 로고
    • Tech. Rep
    • "ITRS 2007 System Driver", Tech. Rep. [Online]. Available: http://www.itrs.net
    • ITRS 2007 System Driver
  • 13
    • 84862328694 scopus 로고    scopus 로고
    • Enhancing effective throughput for transmission line-based bus
    • Sep.
    • A. Carpenter et al., "Enhancing effective throughput for transmission line-based bus", in International Symposium on Computer Architecture, vol. 40, no. 3, Sep. 2012, pp. 165-176.
    • (2012) International Symposium on Computer Architecture , vol.40 , Issue.3 , pp. 165-176
    • Carpenter, A.1
  • 14
    • 34547471544 scopus 로고    scopus 로고
    • Design tradeoffs for tiled CMP on-chip networks
    • DOI 10.1145/1183401.1183430, Proceedings of the 20th Annual International Conference on Supercomputing, ICS 2006
    • J. Balfour and W. J. Dally, "Design tradeoffs for tiled CMP onchip networks", in International Conference on Supercomputing, 2006, pp. 187-198. (Pubitemid 47168505)
    • (2006) Proceedings of the International Conference on Supercomputing , pp. 187-198
    • Balfour, J.1    Dally, W.J.2
  • 16
    • 64949130713 scopus 로고    scopus 로고
    • Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
    • Feb.
    • R. Das et al., "Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs", in International Symposium on High Performance Computer Architecture, Feb. 2009, pp. 175-186.
    • (2009) International Symposium on High Performance Computer Architecture , pp. 175-186
    • Das, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.