-
2
-
-
77949894002
-
-
Ageia Technologies. PhysX by Ageia. http://www.ageia.com/pdf/ds\product\ overview.pdf.
-
PhysX by Ageia
-
-
-
3
-
-
4644295630
-
Evaluating the imagine stream architecture
-
IEEE Computer Society
-
J. H. Ahn, W. J. Dally, B. Khailany, U. J. Kapasi, and A. Das. Evaluating the Imagine Stream Architecture. In ISCA '04: Proceedings of the 31st Annual International Symposium on Computer Architecture, pages 14-25. IEEE Computer Society, 2004.
-
(2004)
ISCA '04: Proceedings of the 31st Annual International Symposium on Computer Architecture
, pp. 14-25
-
-
Ahn, J.H.1
Dally, W.J.2
Khailany, B.3
Kapasi, U.J.4
Das, A.5
-
4
-
-
77949890367
-
-
website
-
ATI website. http://www.ati.com.
-
ATI
-
-
-
5
-
-
27544432558
-
The impact of performance asymmetry in emerging multicore architectures
-
Washington, DC, USA, IEEE Computer Society
-
S. Balakrishnan, R. Rajwar, M. Upton, and K. Lai. The impact of performance asymmetry in emerging multicore architectures. In ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture, pages 506-517, Washington, DC, USA, 2005. IEEE Computer Society.
-
(2005)
ISCA '05: Proceedings of the 32nd Annual International Symposium on Computer Architecture
, pp. 506-517
-
-
Balakrishnan, S.1
Rajwar, R.2
Upton, M.3
Lai, K.4
-
6
-
-
27544482359
-
An architecture framework for transparent instruction set customization in embedded processors
-
IEEE Computer Society
-
N. Clark, J. Blome, M. Chu, S. Mahlke, S. Biles, and K. Flautner. An architecture framework for transparent instruction set customization in embedded processors. In ISCA '05: Proceedings of the 32nd Annual International Symposium on Computer Architecture, pages 272-283. IEEE Computer Society, 2005.
-
(2005)
ISCA '05: Proceedings of the 32nd Annual International Symposium on Computer Architecture
, pp. 272-283
-
-
Clark, N.1
Blome, J.2
Chu, M.3
Mahlke, S.4
Biles, S.5
Flautner, K.6
-
7
-
-
34548354277
-
OptimoDE: Programmable accelerator engines through retargetable customization
-
N. Clark, H. Zhong, K. Fan, S. Mahlke, K. Flautner, and K. V. Nieuwenhove. OptimoDE: Programmable accelerator engines through retargetable customization. In HotChips, 2004.
-
(2004)
HotChips
-
-
Clark, N.1
Zhong, H.2
Fan, K.3
Mahlke, S.4
Flautner, K.5
Nieuwenhove, K.V.6
-
8
-
-
77949881934
-
-
CodeSurfer by, Inc.
-
CodeSurfer by GrammaTech, Inc. http://www.grammatech.com/products/ codesurfer/.
-
GrammaTech
-
-
-
9
-
-
0024866680
-
An efficient method of computing static single assignment form
-
ACM Press
-
R. Cytron, J. Ferrante, B. K. Rosen, M. N.Wegman, and F. K. Zadeck. An efficient method of computing static single assignment form. In POPL '89: Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, pages 25-35. ACM Press, 1989.
-
(1989)
POPL '89: Proceedings of the 16th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages
, pp. 25-35
-
-
Cytron, R.1
Ferrante, J.2
Rosen, B.K.3
Wegman, M.N.4
Zadeck, F.K.5
-
10
-
-
84877083867
-
Merrimac: Supercomputing with streams
-
IEEE Computer Society
-
W. J. Dally, F. Labonte, A. Das, P. Hanrahan, J.-H. Ahn, J. Gummaraju, M. Erez, N. Jayasena, I. Buck, T. J. Knight, and U. J. Kapasi. Merrimac: Supercomputing with streams. In SC '03: Proceedings of the 2003 ACM/IEEE conference on Supercomputing, page 35. IEEE Computer Society, 2003.
-
(2003)
SC '03: Proceedings of the 2003 ACM/IEEE Conference on Supercomputing
, pp. 35
-
-
Dally, W.J.1
Labonte, F.2
Das, A.3
Hanrahan, P.4
Ahn, J.-H.5
Gummaraju, J.6
Erez, M.7
Jayasena, N.8
Buck, I.9
Knight, T.J.10
Kapasi, U.J.11
-
11
-
-
0016116644
-
Design of ion-implanted MOSFET's with very small physical dimensions
-
October
-
R. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc. Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions. In IEEE Journal of Solid-State Circuits, October 1974.
-
(1974)
IEEE Journal of Solid-State Circuits
-
-
Dennard, R.1
Gaensslen, F.H.2
Rideout, V.L.3
Bassous, E.4
Leblanc, A.R.5
-
12
-
-
84955557263
-
RaPiD - Reconfigurable pipelined datapath
-
Springer-Verlag
-
C. Ebeling, D. C. Cronquist, and P. Franklin. RaPiD - reconfigurable pipelined datapath. In FPL '96: Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, pages 126-135. Springer-Verlag, 1996.
-
(1996)
FPL '96: Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
, pp. 126-135
-
-
Ebeling, C.1
Cronquist, D.C.2
Franklin, P.3
-
13
-
-
35448978324
-
Exochi: Architecture and programming environment for a heterogeneous multi-core multithreaded system
-
New York, NY, USA, ACM Press
-
P. W., et al. Exochi: architecture and programming environment for a heterogeneous multi-core multithreaded system. In PLDI '07: Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation, pages 156-166, New York, NY, USA, 2007. ACM Press.
-
(2007)
PLDI '07: Proceedings of the 2007 ACM SIGPLAN Conference on Programming Language Design and Implementation
, pp. 156-166
-
-
P, W.1
-
15
-
-
64849117951
-
Bridging the computation gap between programmable processors and hardwired accelerators
-
Feb.
-
K. Fan, M. Kudlur, G. Dasika, and S. Mahlke. Bridging the computation gap between programmable processors and hardwired accelerators. In HPCA: High Performance Computer Architecture., pages 313-322, Feb. 2009.
-
(2009)
HPCA: High Performance Computer Architecture
, pp. 313-322
-
-
Fan, K.1
Kudlur, M.2
Dasika, G.3
Mahlke, S.4
-
16
-
-
0032674517
-
PipeRench: A coprocessor for streaming multimedia acceleration
-
IEEE Computer Society
-
S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer. PipeRench: A Coprocessor for Streaming Multimedia Acceleration. In ISCA '99: Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 28-39. IEEE Computer Society, 1999.
-
(1999)
ISCA '99: Proceedings of the 26th Annual International Symposium on Computer Architecture
, pp. 28-39
-
-
Goldstein, S.C.1
Schmit, H.2
Moe, M.3
Budiu, M.4
Cadambi, S.5
Taylor, R.R.6
Laufer, R.7
-
17
-
-
17644370078
-
Best of both latency and throughput
-
Washington, DC, USA, IEEE Computer Society
-
E. Grochowski, R. Ronen, J. Shen, and H. Wang. Best of both latency and throughput. In ICCD '04: Proceedings of the IEEE International Conference on Computer Design (ICCD'04), pages 236-243, Washington, DC, USA, 2004. IEEE Computer Society.
-
(2004)
ICCD '04: Proceedings of the IEEE International Conference on Computer Design (ICCD'04)
, pp. 236-243
-
-
Grochowski, E.1
Ronen, R.2
Shen, J.3
Wang, H.4
-
18
-
-
0031360911
-
Garp: A MIPS processor with a reconfigurable coprocessor
-
K. L. Pocek and J. Arnold, editors, IEEE Computer Society Press
-
J. R. Hauser and J. Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor. In K. L. Pocek and J. Arnold, editors, FCCM '97: IEEE Symposium on FPGAs for Custom Computing Machines, pages 12-21. IEEE Computer Society Press, 1997.
-
(1997)
FCCM '97: IEEE Symposium on FPGAs for Custom Computing Machines
, pp. 12-21
-
-
Hauser, J.R.1
Wawrzynek, J.2
-
19
-
-
33847708700
-
Scaling, power, and the future of CMOS
-
M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein. Scaling, Power, and the Future of CMOS. In IEDM '05: IEEE International Electron Devices Meeting, 2005.
-
(2005)
IEDM '05: IEEE International Electron Devices Meeting
-
-
Horowitz, M.1
Alon, E.2
Patil, D.3
Naffziger, S.4
Kumar, R.5
Bernstein, K.6
-
21
-
-
1542299262
-
Energy characterization of a tiled architecture processor with on-chip networks
-
San Diego, CA, USA, August
-
J. S. Kim, M. B. Taylor, J. Miller, and D. Wentzlaff. Energy characterization of a tiled architecture processor with on-chip networks. In International Symposium on Low Power Electronics and Design, San Diego, CA, USA, August 2003.
-
(2003)
International Symposium on Low Power Electronics and Design
-
-
Kim, J.S.1
Taylor, M.B.2
Miller, J.3
Wentzlaff, D.4
-
22
-
-
4644370318
-
Single-ISA heterogeneous multi-core architectures for multithreaded workload performance
-
IEEE Computer Society
-
R. Kumar, D. M. Tullsen, P. Ranganathan, N. P. Jouppi, and K. I. Farkas. Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. In ISCA '04: Proceedings of the 31st Annual International Symposium on Computer Architecture, page 64. IEEE Computer Society, 2004.
-
(2004)
ISCA '04: Proceedings of the 31st Annual International Symposium on Computer Architecture
, pp. 64
-
-
Kumar, R.1
Tullsen, D.M.2
Ranganathan, P.3
Jouppi, N.P.4
Farkas, K.I.5
-
24
-
-
34548142850
-
Power-performance considerations of parallel computing on chip multiprocessors
-
J. Li and J. F. Martínez. Power-performance considerations of parallel computing on chip multiprocessors. ACM Trans. Archit. Code Optim., 2(4):397-422, 2005.
-
(2005)
ACM Trans. Archit. Code Optim.
, vol.2
, Issue.4
, pp. 397-422
-
-
Li, J.1
Martínez, J.F.2
-
25
-
-
77949891093
-
-
June, Equator Technologies
-
MAP-CA datasheet, June 2001. Equator Technologies.
-
(2001)
MAP-CA Datasheet
-
-
-
26
-
-
77949881413
-
-
MIPS Technologies. MIPS Technologies product page. http://www.mips.com/ products/processors/32-64-bit-cores/mips32-24ke, 2008- 2009.
-
(2008)
MIPS Technologies Product Page
-
-
-
27
-
-
33846498579
-
Tartan: Evaluating spatial computation for whole program execution
-
M. Mishra, T. J. Callahan, T. Chelcea, G. Venkataramani, S. C. Goldstein, and M. Budiu. Tartan: evaluating spatial computation for whole program execution. SIGOPS Oper. Syst. Rev., 40(5):163-174, 2006.
-
(2006)
SIGOPS Oper. Syst. Rev.
, vol.40
, Issue.5
, pp. 163-174
-
-
Mishra, M.1
Callahan, T.J.2
Chelcea, T.3
Venkataramani, G.4
Goldstein, S.C.5
Budiu, M.6
-
28
-
-
77949908004
-
-
website
-
nVidia website. http://www.nvidia.com.
-
NVidia
-
-
-
29
-
-
77949891830
-
-
Website
-
OpenImpact Website. http://gelato.uiuc.edu/.
-
OpenImpact
-
-
-
30
-
-
25844479498
-
A survey of general-purpose computation on graphics hardware
-
August
-
J. D. Owens, D. Luebke, N. Govindaraju, M. Harris, J. Krger, A. E. Lefohn, and T. J. Purcell. A survey of general-purpose computation on graphics hardware. In Eurographics 2005, State of the Art Reports, pages 21-51, August 2005.
-
(2005)
Eurographics 2005, State of the Art Reports
, pp. 21-51
-
-
Owens, J.D.1
Luebke, D.2
Govindaraju, N.3
Harris, M.4
Krger, J.5
Lefohn, A.E.6
Purcell, T.J.7
-
31
-
-
0031096193
-
A case for intelligent RAM
-
April
-
D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick. A case for intelligent RAM. IEEE Micro, 17(2):34-44, April 1997.
-
(1997)
IEEE Micro
, vol.17
, Issue.2
, pp. 34-44
-
-
Patterson, D.1
Anderson, T.2
Cardwell, N.3
Fromm, R.4
Keeton, K.5
Kozyrakis, C.6
Thomas, R.7
Yelick, K.8
-
32
-
-
0004049036
-
-
TM1000 preliminary data book, 1997. http://www.semiconductors.philips. com/acrobat/other/tm1000.pdf.
-
(1997)
TM1000 Preliminary Data Book
-
-
-
34
-
-
34547205574
-
Efficient architectures through application clustering and architectural heterogeneity
-
New York, NY, USA, ACM Press
-
L. Strozek and D. Brooks. Efficient architectures through application clustering and architectural heterogeneity. In CASES '06: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, pages 190-200, New York, NY, USA, 2006. ACM Press.
-
(2006)
CASES '06: Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems
, pp. 190-200
-
-
Strozek, L.1
Brooks, D.2
-
35
-
-
34249721013
-
The wavescalar architecture
-
S. Swanson, A. Schwerin, M. Mercaldi, A. Petersen, A. Putnam, K. Michelson, M. Oskin, and S. J. Eggers. The wavescalar architecture. ACM Trans. Comput. Syst., 25(2):4, 2007.
-
(2007)
ACM Trans. Comput. Syst.
, vol.25
, Issue.2
, pp. 4
-
-
Swanson, S.1
Schwerin, A.2
Mercaldi, M.3
Petersen, A.4
Putnam, A.5
Michelson, K.6
Oskin, M.7
Eggers, S.J.8
-
36
-
-
4644353790
-
Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ILP and streams
-
IEEE Computer Society
-
M. B. Taylor, W. Lee, J. Miller, D. Wentzlaff, I. Bratt, B. Greenwald, H. Hoffmann, P. Johnson, J. Kim, J. Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agarwal. Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. In ISCA '04: Proceedings of the 31st annual International Symposium on Computer Architecture, page 2. IEEE Computer Society, 2004.
-
(2004)
ISCA '04: Proceedings of the 31st Annual International Symposium on Computer Architecture
, pp. 2
-
-
Taylor, M.B.1
Lee, W.2
Miller, J.3
Wentzlaff, D.4
Bratt, I.5
Greenwald, B.6
Hoffmann, H.7
Johnson, P.8
Kim, J.9
Psota, J.10
Saraf, A.11
Shnidman, N.12
Strumpen, V.13
Frank, M.14
Amarasinghe, S.15
Agarwal, A.16
-
37
-
-
77957937869
-
-
Cacti 5.1., Palo Alto
-
S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi. Cacti 5.1. Technical Report HPL-2008-20, HP Labs, Palo Alto, 2008.
-
(2008)
Technical Report HPL-2008-20, HP Labs
-
-
Thoziyoor, S.1
Muralimanohar, N.2
Ahn, J.H.3
Jouppi, N.P.4
-
38
-
-
0034846651
-
Hardware/software instruction set configurability for system-on-chip processors
-
ACM Press
-
A. Wang, E. Killian, D. Maydan, and C. Rowen. Hardware/software instruction set configurability for system-on-chip processors. In DAC '01: Proceedings of the 38th conference on Design automation, pages 184-188. ACM Press, 2001.
-
(2001)
DAC '01: Proceedings of the 38th Conference on Design Automation
, pp. 184-188
-
-
Wang, A.1
Killian, E.2
Maydan, D.3
Rowen, C.4
-
40
-
-
0033703884
-
CHIMAERA: A high-performance architecture with a tightly-coupled reconfigurable functional unit
-
ACM Press
-
Z. A. Ye, A. Moshovos, S. Hauck, and P. Banerjee. CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit. In ISCA '00: Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 225-235. ACM Press, 2000.
-
(2000)
ISCA '00: Proceedings of the 27th Annual International Symposium on Computer Architecture
, pp. 225-235
-
-
Ye, Z.A.1
Moshovos, A.2
Hauck, S.3
Banerjee, P.4
-
41
-
-
64949084227
-
Reconciling specialization and flexibility through compound circuits
-
Feb.
-
S. Yehia, S. Girbal, H. Berry, and O. Temam. Reconciling specialization and flexibility through compound circuits. In HPCA 15: High Performance Computer Architecture, pages 277-288, Feb. 2009.
-
(2009)
HPCA 15: High Performance Computer Architecture
, pp. 277-288
-
-
Yehia, S.1
Girbal, S.2
Berry, H.3
Temam, O.4
|