BiN: A buffer-in-NUCA scheme for accelerator-rich CMPs

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2012, Pages 225-230

  Cong, Jason ^a   Ghodrat, Mohammad Ali ^a   Gill, Michael ^a   Liu, Chunyue ^a   Reinman, Glenn ^a  

^a Engineering IV   (United States)

Author keywords

accelerator; cache; cmp; memory

Indexed keywords

BUFFER ALLOCATION; BUFFER SIZES; BUFFER SPACE; CACHE; CMP; DISTRIBUTED CACHE; NON-UNIFORM CACHE ARCHITECTURES; ON CHIPS; POWER-EFFICIENCY; SHARED BUFFER;

BINS; DATA STORAGE EQUIPMENT; LOW POWER ELECTRONICS; PARTICLE ACCELERATORS;

ACCELERATION;

EID: 84865564683     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2333660.2333715     Document Type: Conference Paper

References (19)

1. C. Johnson et al. A wire-speed power™ processor: 2.3ghz 45nm soi with 16 cores and 64 threads. ISSCC 2010.
2. L. Seiler et al. Larrabee: a many-core x86 architecture for visual computing. IEEE Micro, 29(1):10-21, 2009.
3. J. Cong et al. AXR-CMP: architecture support in accelerator-rich CMPs. Workshop on SoC Architecture, Accelerators and Workloads 2011.
4. J. Cong et al. Architecture support for accelerator-rich CMPs. DAC 2012.
5. ITRS 2007 system drivers. http://www.itrs.net/.
6. M. J. Lyonsy et al. The Accelerator Store: a shared memory framework for accelerator-based systems. ACM Trans. Architecture and Code Optimization, 8(4):48, 2012.
7. C. F. Fajardo et al. Buffer-Integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms. DAC 2011.
8. J. Cong et al. An energy-efficient adaptive hybrid cache. ISLPED 2011.
9. J. Cong et al. Combined loop transformation and hierarchy allocation for data reuse optimization. ICCAD 2011.
10. A. Bui et al. Platform characterization for domain-specific computing. ASPDAC 2012.
11. B. M. Beckmann et al. ASR: adaptive selective replication for CMP Caches. MICRO 2006.
12. S. Cho and L. Jin. Managing distributed, shared L2 caches through OS-level page allocation. MICRO 2006.
13. J. Cong et al. A shared Buffer-in-NUCA management scheme for accelerator-rich CMPs. University of California, Los Angeles Computer Science Department Technical Report 120012, 2012.
14. M. Qureshi and Y. Patt. Utility-based cache partitioning: a low-overhead, high-performance, runtime mechanism to partition shared caches. MICRO 2006.
15. HP Cacti, http://quid.hpl.hp.com:9081/cacti/.
16. P. S. Magnusson et al. Simics: a full system simulation platform. IEEE Trans. Computer, 35(2):50-58, 2002.
17. M. M. K. Martin et al. Multifacet's general execution-driven multiprocessor simulator toolset. ACM SIGARCH Computer Architecture News, 33(4):92-99, 2005.
18. J. Cong et al. High-level synthesis for FPGAs: from prototyping to deployment. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 30(4):473-491, 2011.
19. S. Li et al. McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. MICRO 2009.