The accelerator store: A shared memory framework for accelerator-based systems

Transactions on Architecture and Code Optimization

Volumn 8, Issue 4, 2012, Pages

  Lyons, Michael J ^a   Hempstead, Mark ^b   Wei, Gu Yeon ^a   Brooks, David ^a  

^a HARVARD UNIVERSITY   (United States)

^b DREXEL UNIVERSITY   (United States)

Author keywords

Hardware acceleration; Low power; Memory systems; Shared memory

Indexed keywords

ARCHITECTURAL COMPONENTS; AREA REDUCTION; DESIGN APPROACHES; HARDWARE ACCELERATION; HARDWARE ACCELERATORS; LOW POWER; MEMORY SYSTEMS; MULTICORE ARCHITECTURES; POWER EFFICIENT; RESEARCH DIRECTIONS; SHARED MEMORIES; SRAM MEMORIES; SYSTEM ON CHIPS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE;

ACCELERATION;

EID: 84857883486     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/2086696.2086727     Document Type: Article

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