ATree-based topology synthesis for on-chip network

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2011, Pages 651-658

  Cong, Jason ^a   Huang, Yuhui ^a   Yuan, Bo ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HYBRID NETWORK; INTERCONNECT NETWORKS; MULTI-PROCESSORS; NETWORK ON CHIP; NETWORK RESOURCE; ON-CHIP NETWORKS; POWER MINIMIZATION; SHORTEST PATH; STEINER ARBORESCENCE; SYNTHESIS ALGORITHMS; SYSTEM-ON-A-CHIP; TOPOLOGY SYNTHESIS;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUSES; COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS; TOPOLOGY; VLSI CIRCUITS;

ROUTERS;

EID: 84862915062     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2011.6105399     Document Type: Conference Paper

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