메뉴 건너뛰기




Volumn 48, Issue 5, 2013, Pages 1276-1289

A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O transceiver in 65 nm CMOS

Author keywords

High speed I O; Injection locked oscillator; Low power; Low voltage regulator; Poly phase filter; Transceiver; Voltage mode driver

Indexed keywords

HIGH SPEED I/O; INJECTION LOCKED OSCILLATORS; LOW POWER; LOW-VOLTAGE; POLY-PHASE FILTERS; VOLTAGE MODE;

EID: 84893001660     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2013.2249812     Document Type: Article
Times cited : (47)

References (23)
  • 1
    • 78650062073 scopus 로고    scopus 로고
    • A 47 x 10 Gb/s 1.4 mW/Gb/s parallel interface in 45 nm CMOS
    • Dec.
    • F. O'Mahoney, J. E. Jaussi, and J. Kennedy et al., "A 47 x 10 Gb/s 1.4 mW/Gb/s parallel interface in 45 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2828-2837, Dec. 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , Issue.12 , pp. 2828-2837
    • O'Mahoney, F.1    Jaussi, J.E.2    Kennedy, J.3
  • 2
    • 77950252885 scopus 로고    scopus 로고
    • A 0.6 mW/Gb/s, 6.4-7.2 Gb/s serial link receiver using local injection-locked ring oscillators in 90 nm CMOS
    • Apr.
    • K. Hu, T. Jiang, J. Wang, F. O'Mahony, and P. Y. Chiang, "A 0.6 mW/Gb/s, 6.4-7.2 Gb/s serial link receiver using local injection-locked ring oscillators in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 899-908, Apr. 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , Issue.4 , pp. 899-908
    • Hu, K.1    Jiang, T.2    Wang, J.3    O'Mahony, F.4    Chiang, P.Y.5
  • 3
    • 60649103812 scopus 로고    scopus 로고
    • Clocking analysis, implementation and measurement techniques for high-speed data links - A tutorial
    • Jan.
    • B. Casper and F. O'Mahony, "Clocking analysis, implementation and measurement techniques for high-speed data links - A tutorial," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 1, pp. 17-39, Jan. 2009.
    • (2009) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.56 , Issue.1 , pp. 17-39
    • Casper, B.1    O'Mahony, F.2
  • 4
    • 79955728572 scopus 로고    scopus 로고
    • A highly digital 0.57-4 Gb/s 1.9 mW/Gb/s serial-link transceiver using currect-recycling in 90 nm CMOS
    • R. Inti et al., "A highly digital 0.57-4 Gb/s 1.9 mW/Gb/s serial-link transceiver using currect-recycling in 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2011, pp. 152-153.
    • (2011) IEEE ISSCC Dig. Tech. Papers , pp. 152-153
    • Inti, R.1
  • 5
    • 75649145360 scopus 로고    scopus 로고
    • Technologies for ultradynamic voltage scaling
    • A. P. Chandrakasan et al., "Technologies for ultradynamic voltage scaling," Proc. IEEE, vol. 98, no. 2, pp. 191-214, Feb. 2010.
    • (2010) Proc. IEEE , vol.98 , Issue.2
    • Chandrakasan, A.P.1
  • 6
    • 0036857082 scopus 로고    scopus 로고
    • Adaptive supply serial links with sub-1 V operation and per-pin clock recovery
    • Nov.
    • J. Kim and M. Horowitz, "Adaptive supply serial links with sub-1 V operation and per-pin clock recovery," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1403-1413, Nov. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.11 , pp. 1403-1413
    • Kim, J.1    Horowitz, M.2
  • 7
    • 78650047611 scopus 로고    scopus 로고
    • A 4.5 mW/Gb/s 6.4 Gb/s 22+1-lane source synchronous receiver core with optional cleanup PLL in 65 nm CMOS
    • Dec.
    • R. Reutemann et al., "A 4.5 mW/Gb/s 6.4 Gb/s 22+1-lane source synchronous receiver core with optional cleanup PLL in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2850-2860, Dec. 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , Issue.12 , pp. 2850-2860
    • Reutemann, R.1
  • 8
    • 0030400848 scopus 로고    scopus 로고
    • A 0.8 μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links
    • Dec.
    • C.-K. Yang and M. Horowitz, "A 0.8 μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 2015-2023, Dec. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.12 , pp. 2015-2023
    • Yang, C.-K.1    Horowitz, M.2
  • 9
    • 63449125471 scopus 로고    scopus 로고
    • A 16 Gb/s/link, 64 GB/s bidirectional asymmetric memory interface
    • Apr.
    • H. Lee et al., "A 16 Gb/s/link, 64 GB/s bidirectional asymmetric memory interface," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1235-1247, Apr. 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.4 , pp. 1235-1247
    • Lee, H.1
  • 10
    • 57849158609 scopus 로고    scopus 로고
    • A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS
    • Dec.
    • J. Poulton et al., "A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2745-2757, Dec. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.12 , pp. 2745-2757
    • Poulton, J.1
  • 11
    • 41549163921 scopus 로고    scopus 로고
    • A scalable 5-15 Gbps, 14-75 mW low power I/O transceiver in 65 nm CMOS
    • Apr.
    • G. Balamurugan, J. Kennedy, and G. Banerjee et al., "A scalable 5-15 Gbps, 14-75 mW low power I/O transceiver in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 1010-1019, Apr. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.4 , pp. 1010-1019
    • Balamurugan, G.1    Kennedy, J.2    Banerjee, G.3
  • 12
    • 77952185910 scopus 로고    scopus 로고
    • A 12.3 mW 12.5 Gb/s complete transceiver in 65 nm CMOS
    • K. Fukuda et al., "A 12.3 mW 12.5 Gb/s complete transceiver in 65 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 368-369.
    • (2010) IEEE ISSCC Dig. Tech. Papers , pp. 368-369
    • Fukuda, K.1
  • 13
    • 84892965155 scopus 로고    scopus 로고
    • A design methodology for power efficiency optimization of high-speed equalized-electrical I/O architectures
    • early access
    • A. Palaniappan and S. Palermo, "A design methodology for power efficiency optimization of high-speed equalized-electrical I/O architectures," IEEE Trans. VLSI Systems, 2012, early access.
    • (2012) IEEE Trans. VLSI Systems
    • Palaniappan, A.1    Palermo, S.2
  • 16
    • 34548852188 scopus 로고    scopus 로고
    • A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time
    • D. Schinkel et al., "A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 314-605.
    • (2007) IEEE ISSCC Dig. Tech. Papers , pp. 314-605
    • Schinkel, D.1
  • 17
    • 84864754237 scopus 로고    scopus 로고
    • 0.16-0.25 pJ/bit, 8 Gb/s near-threshold serial link receiver with super-harmonic injection locking
    • Aug.
    • K. Hu et al., "0.16-0.25 pJ/bit, 8 Gb/s near-threshold serial link receiver with super-harmonic injection locking," IEEE J. Solid-State Circuits, vol. 47, no. 8, pp. 1842-1853, Aug. 2012.
    • (2012) IEEE J. Solid-State Circuits , vol.47 , Issue.8 , pp. 1842-1853
    • Hu, K.1
  • 20
    • 34548819354 scopus 로고    scopus 로고
    • A 16 Gb/s source-series terminated transmitter in 65 nm CMOS SOI
    • C. Menolfi et al., "A 16 Gb/s source-series terminated transmitter in 65 nm CMOS SOI," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 446-447.
    • (2007) IEEE ISSCC Dig. Tech. Papers , pp. 446-447
    • Menolfi, C.1
  • 21
    • 84865392897 scopus 로고    scopus 로고
    • A 6-Gbit/s hybrid voltage-mode transmitter with current-mode equalization in 90-nm CMOS
    • Aug.
    • Y.-H. Song and S. Palermo, "A 6-Gbit/s hybrid voltage-mode transmitter with current-mode equalization in 90-nm CMOS," IEEE Trans. Circuits Syst. II, vol. 59, no. 8, pp. 491-495, Aug. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.8 , pp. 491-495
    • Song, Y.-H.1    Palermo, S.2
  • 22
    • 79957634446 scopus 로고    scopus 로고
    • 7.4 Gb/s 6.8 mW source synchronous receiver in 65 nm CMOS
    • Jun
    • M. Hossain and A. C. Carusone, "7.4 Gb/s 6.8 mW source synchronous receiver in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1337-1348, Jun 2011.
    • (2011) IEEE J. Solid-State Circuits , vol.46 , Issue.6 , pp. 1337-1348
    • Hossain, M.1    Carusone, A.C.2
  • 23
    • 84860657238 scopus 로고    scopus 로고
    • A 28 Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32 nm SOI CMOS technology
    • J. Bulzacchelli et al., "A 28 Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32 nm SOI CMOS technology," in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 324-325.
    • (2012) IEEE ISSCC Dig. Tech. Papers , pp. 324-325
    • Bulzacchelli, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.