A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 152-153

  Inti, Rajesh ^a   Elshazly, Amr ^a   Young, Brian ^a   Yin, Wenjing ^a   Kossel, Marcel ^b   Toifl, Thomas ^b   Hanumolu, Pavan Kumar ^a  

^a OREGON STATE UNIVERSITY   (United States)

^b IBM RESEARCH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; RECYCLING; TRANSCEIVERS;

COMMUNICATION BANDWIDTH; DC-DC CONVERSION; ENERGY EFFICIENT; HIGH-EFFICIENCY; POWER EFFICIENCY; SERIAL-LINK TRANSCEIVER; SHORT CHANNELS; SUPPLY VOLTAGES;

DC-DC CONVERTERS;

EID: 79955728572     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746260     Document Type: Conference Paper

References (5)

1. J. Kim and M.A. Horowitz, "Adaptive Supply Serial Links with Sub-1V Operation and Per-Pin Clock Recovery," ISSCC Dig. Tech. Papers, pp. 268-269, Feb., 2002.
2. G. Balamurugan, J. Kennedy, G. Banerjee, J.E. Jaussi, M. Mansuri, F. O'Mahony, B. Casper, and R. Mooney, "A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 1010-1019, April, 2008.
3. S. Rajapandian, Z. Xu, and K.L. Shepard, "Implicit DC-DC Down Conversion Through Charge-Recycling," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 846-852, April, 2005.
4. R. Palmer, J. Poulton, W. J. Dally, J. Eyles, A.M. Fuller, T. Greer, and M.A. Horowitz, "A 14mW 6.25 Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications," ISSCC Dig. Tech. Papers, pp. 440-441, Feb., 2007.
5. K.L.J. Wong, M. Mansuri, H.Hatamkhani, and C.K.K. Yang, "A 27mW 3.6-Gb/s I/O Transceiver," Symp. VLSI circuits, pp. 99-102, Feb., 2003.