Distributed runtime computation of constraints for multiple inner loops

Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013

Volumn , Issue , 2013, Pages 389-395

  Farahini, Nasim ^a   Hemani, Ahmed ^a   Paul, Kolin ^b  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^b INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

CGRA; Code compaction; Inner loop acceleration; Streaming address generation

Indexed keywords

ADDRESS GENERATION; CGRA; CODE COMPACTION; DISTRIBUTED IMPLEMENTATION; DISTRIBUTED RUNTIME; HARDWARE SOLUTIONS; INNER LOOPS; PERFORMANCE PENALTIES;

CLOSED LOOP CONTROL SYSTEMS; HARDWARE; SIGNAL PROCESSING; SYSTEMS ANALYSIS;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 84890042733     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2013.49     Document Type: Conference Paper

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