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Volumn 95, Issue 7, 2008, Pages 761-776

MT-ADRES: Multi-threading on coarse-grained reconfigurable architecture

Author keywords

Methodology; Multi threading

Indexed keywords

ARCHITECTURE; INTEGRATED CIRCUITS; MOTION PICTURE EXPERTS GROUP STANDARDS; TELLURIC PROSPECTING;

EID: 49149131310     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/00207210802213930     Document Type: Conference Paper
Times cited : (9)

References (14)
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    • Akkary, H., and Driscoll, M.A. (1998), "A Dynamic Multi-threading Processor," in 31st Annual ACM/IEEE International Symposium on Microarchitecture. MICRO-31. Proceedings 30 November-2 December, pp. 226-236.
  • 2
    • 85060036181 scopus 로고
    • Validity of the Single Processor Approach to Achieve Large-scale Computing Capabilities
    • Amdahl, G.M. (1967), "Validity of the Single Processor Approach to Achieve Large-scale Computing Capabilities," in Proceedings in AFIPS Spring Joint Computer Conference 30, pp. 483-485.
    • (1967) Proceedings in AFIPS Spring Joint Computer Conference , vol.30 , pp. 483-485
    • Amdahl, G.M.1
  • 3
    • 3242815471 scopus 로고    scopus 로고
    • Scaling to the end of Silicon with EDGE Architectures
    • Burger, D., Keckler, S.W., and McKinley, K.S. (2004), "Scaling to the end of Silicon with EDGE Architectures," IEEE Computer, 37, 44-55.
    • (2004) IEEE Computer , vol.37 , pp. 44-55
    • Burger, D.1    Keckler, S.W.2    McKinley, K.S.3
  • 6
    • 0031237789 scopus 로고    scopus 로고
    • Simultaneous Multi-threading: A Platform for Next-Generation Processors
    • Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L., and Tullsen, D.M. (1997), "Simultaneous Multi-threading: A Platform for Next-Generation Processors," Micro IEEE, 17, 12-19.
    • (1997) Micro IEEE , vol.17 , pp. 12-19
    • Eggers, S.J.1    Emer, J.S.2    Levy, H.M.3    Lo, J.L.4    Stamm, R.L.5    Tullsen, D.M.6
  • 10
    • 33746874318 scopus 로고    scopus 로고
    • A Coarse-grained Reconfigurable Architecture Template and its Compilation Techniques,
    • Ph.D. thesis, IMEC, Belgium
    • Mei, B. (2005), "A Coarse-grained Reconfigurable Architecture Template and its Compilation Techniques," Ph.D. thesis, IMEC, Belgium.
    • (2005)
    • Mei, B.1
  • 11
    • 34548098766 scopus 로고    scopus 로고
    • A New Multi-Bank Memory Organization to Reduce Bank Conflicts in Coarse-Grained Reconfigurable Architectures,
    • IMEC, Technical report
    • Mei, B., Kim, S., and Pasko, R. (2006), "A New Multi-Bank Memory Organization to Reduce Bank Conflicts in Coarse-Grained Reconfigurable Architectures," IMEC, Technical report.
    • (2006)
    • Mei, B.1    Kim, S.2    Pasko, R.3
  • 12
    • 30344464097 scopus 로고    scopus 로고
    • High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm
    • Ozer, E., and Conte, T.M. (2005), "High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm," IEEE Transactions on Parallel and Distributed Systems, 16, 1132-1142.
    • (2005) IEEE Transactions on Parallel and Distributed Systems , vol.16 , pp. 1132-1142
    • Ozer, E.1    Conte, T.M.2
  • 13
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    • Coupling of a Reconfigurable Architecture and a Multithreaded Processor Core with Integrated Real-Time Scheduling
    • IPDPS, April 25-29, p
    • Uhrig, S., Maier, S., Kuzmanov, G., and Ungerer, T. (2006), "Coupling of a Reconfigurable Architecture and a Multithreaded Processor Core with Integrated Real-Time Scheduling," in International Parallel and Distributed Processing Symposium. IPDPS, April 25-29, p. 4.
    • (2006) International Parallel and Distributed Processing Symposium , pp. 4
    • Uhrig, S.1    Maier, S.2    Kuzmanov, G.3    Ungerer, T.4
  • 14
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    • Zalamea, J., Llosa, J., Ayguade, E., and Valero, M. (2003), Hierarchical Clustered Register File Organization for VLIW Processors, in International Parallel and Distributed Processing Symposium, Proceedings, April 22-26, p. 10.
    • Zalamea, J., Llosa, J., Ayguade, E., and Valero, M. (2003), "Hierarchical Clustered Register File Organization for VLIW Processors," in International Parallel and Distributed Processing Symposium, Proceedings, April 22-26, p. 10.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.