-
1
-
-
0032315403
-
-
Akkary, H., and Driscoll, M.A. (1998), A Dynamic Multi-threading Processor, in 31st Annual ACM/IEEE International Symposium on Microarchitecture. MICRO-31. Proceedings 30 November-2 December, pp. 226-236.
-
Akkary, H., and Driscoll, M.A. (1998), "A Dynamic Multi-threading Processor," in 31st Annual ACM/IEEE International Symposium on Microarchitecture. MICRO-31. Proceedings 30 November-2 December, pp. 226-236.
-
-
-
-
2
-
-
85060036181
-
Validity of the Single Processor Approach to Achieve Large-scale Computing Capabilities
-
Amdahl, G.M. (1967), "Validity of the Single Processor Approach to Achieve Large-scale Computing Capabilities," in Proceedings in AFIPS Spring Joint Computer Conference 30, pp. 483-485.
-
(1967)
Proceedings in AFIPS Spring Joint Computer Conference
, vol.30
, pp. 483-485
-
-
Amdahl, G.M.1
-
3
-
-
3242815471
-
Scaling to the end of Silicon with EDGE Architectures
-
Burger, D., Keckler, S.W., and McKinley, K.S. (2004), "Scaling to the end of Silicon with EDGE Architectures," IEEE Computer, 37, 44-55.
-
(2004)
IEEE Computer
, vol.37
, pp. 44-55
-
-
Burger, D.1
Keckler, S.W.2
McKinley, K.S.3
-
4
-
-
0026993183
-
Partitioned Register Files for VLIWs: A Preliminary Analysis of Tradeoffs
-
Portland, OR, USA, pp
-
Capitanio, A., Dutt, N., and Nicolau, A. (1992), "Partitioned Register Files for VLIWs: A Preliminary Analysis of Tradeoffs," in The 25th Annual International Symposium on Microarchitecture. Portland, OR, USA, pp. 292-300.
-
(1992)
The 25th Annual International Symposium on Microarchitecture
, pp. 292-300
-
-
Capitanio, A.1
Dutt, N.2
Nicolau, A.3
-
5
-
-
33646393297
-
CUSTARD - a Customisable Threaded FPGA Soft Processor and Tools
-
Tempere, Finland, August 24-26, pp
-
Dimond, R., Mencer, O., and Luk, W. (2005), "CUSTARD - a Customisable Threaded FPGA Soft Processor and Tools," in International Conference on Field Programmable Logic and Applications, Tempere, Finland, August 24-26, pp. 1-6.
-
(2005)
International Conference on Field Programmable Logic and Applications
, pp. 1-6
-
-
Dimond, R.1
Mencer, O.2
Luk, W.3
-
6
-
-
0031237789
-
Simultaneous Multi-threading: A Platform for Next-Generation Processors
-
Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L., and Tullsen, D.M. (1997), "Simultaneous Multi-threading: A Platform for Next-Generation Processors," Micro IEEE, 17, 12-19.
-
(1997)
Micro IEEE
, vol.17
, pp. 12-19
-
-
Eggers, S.J.1
Emer, J.S.2
Levy, H.M.3
Lo, J.L.4
Stamm, R.L.5
Tullsen, D.M.6
-
7
-
-
4243510239
-
Exploiting Coarse-Grain Parallelism in the MPEG-2 Algorithm,
-
CSL-TR-98-771, September
-
Iwata, E., and Olukotun, K. (1998), "Exploiting Coarse-Grain Parallelism in the MPEG-2 Algorithm," Stanford University Computer Systems Lab Technical Report CSL-TR-98-771, September.
-
(1998)
Stanford University Computer Systems Lab Technical Report
-
-
Iwata, E.1
Olukotun, K.2
-
8
-
-
84962791602
-
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
-
Hong Kong, December, pp
-
Mei, B., Vernalde, S., Verkest, D., Man, H.D., and Lauwereins, R. (2002), "ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix," in International Conference on Field Programmable Technology, Hong Kong, December, pp. 166-173.
-
(2002)
International Conference on Field Programmable Technology
, pp. 166-173
-
-
Mei, B.1
Vernalde, S.2
Verkest, D.3
Man, H.D.4
Lauwereins, R.5
-
9
-
-
84962791602
-
DRESC: A Retargetable Compiler for Coarse-Grained Reconfigurable Architectures
-
Montpellier, France
-
Mei, B., Vernalde, S., Verkest, D., Man, H.D., and Lauwereins, R. (2003), "DRESC: A Retargetable Compiler for Coarse-Grained Reconfigurable Architectures," 12th International Conference on Field Programmable Logic and Applications, FPL 2002, Montpellier, France.
-
(2002)
12th International Conference on Field Programmable Logic and Applications, FPL
-
-
Mei, B.1
Vernalde, S.2
Verkest, D.3
Man, H.D.4
Lauwereins, R.5
-
10
-
-
33746874318
-
A Coarse-grained Reconfigurable Architecture Template and its Compilation Techniques,
-
Ph.D. thesis, IMEC, Belgium
-
Mei, B. (2005), "A Coarse-grained Reconfigurable Architecture Template and its Compilation Techniques," Ph.D. thesis, IMEC, Belgium.
-
(2005)
-
-
Mei, B.1
-
11
-
-
34548098766
-
A New Multi-Bank Memory Organization to Reduce Bank Conflicts in Coarse-Grained Reconfigurable Architectures,
-
IMEC, Technical report
-
Mei, B., Kim, S., and Pasko, R. (2006), "A New Multi-Bank Memory Organization to Reduce Bank Conflicts in Coarse-Grained Reconfigurable Architectures," IMEC, Technical report.
-
(2006)
-
-
Mei, B.1
Kim, S.2
Pasko, R.3
-
12
-
-
30344464097
-
High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm
-
Ozer, E., and Conte, T.M. (2005), "High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm," IEEE Transactions on Parallel and Distributed Systems, 16, 1132-1142.
-
(2005)
IEEE Transactions on Parallel and Distributed Systems
, vol.16
, pp. 1132-1142
-
-
Ozer, E.1
Conte, T.M.2
-
13
-
-
33847122203
-
Coupling of a Reconfigurable Architecture and a Multithreaded Processor Core with Integrated Real-Time Scheduling
-
IPDPS, April 25-29, p
-
Uhrig, S., Maier, S., Kuzmanov, G., and Ungerer, T. (2006), "Coupling of a Reconfigurable Architecture and a Multithreaded Processor Core with Integrated Real-Time Scheduling," in International Parallel and Distributed Processing Symposium. IPDPS, April 25-29, p. 4.
-
(2006)
International Parallel and Distributed Processing Symposium
, pp. 4
-
-
Uhrig, S.1
Maier, S.2
Kuzmanov, G.3
Ungerer, T.4
-
14
-
-
84947286374
-
-
Zalamea, J., Llosa, J., Ayguade, E., and Valero, M. (2003), Hierarchical Clustered Register File Organization for VLIW Processors, in International Parallel and Distributed Processing Symposium, Proceedings, April 22-26, p. 10.
-
Zalamea, J., Llosa, J., Ayguade, E., and Valero, M. (2003), "Hierarchical Clustered Register File Organization for VLIW Processors," in International Parallel and Distributed Processing Symposium, Proceedings, April 22-26, p. 10.
-
-
-
|