A fast-locking ADPLL with instantaneous restart capability in 28-nm CMOS technology

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 60, Issue 11, 2013, Pages 741-745

  Höppner, Sebastian ^a   Haenzsche, Stefan ^a   Ellguth, Georg ^a   Walter, Dennis ^a   Eisenreich, Holger ^a   Schüffny, René ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

All digital phase locked loop (ADPLL); Bang bang phase frequency detector (PFD); Clock generator; Lock time

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; JITTER; PHASE COMPARATORS; PHASE LOCKED LOOPS; SEMICONDUCTOR DEVICE MANUFACTURE; SYSTEM-ON-CHIP;

ACCUMULATED JITTER; ALL DIGITAL PHASE LOCKED LOOP; CLOCK GENERATOR; INSTANTANEOUS PHASE; LOCK TIME; MULTIPROCESSOR SYSTEM ON CHIPS; PHASE FREQUENCY DETECTORS; PHASE SYNCHRONIZATION;

LOCKS (FASTENERS);

EID: 84888341057     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2013.2278123     Document Type: Article

References (13)

1. M. Winter, S. Kunze, E. Adeva, B. Mennenga, E. Matus, G. Fettweis, H. Eisenreich, G. Ellguth, S. Höppner, S. Scholze, R. Schüffny, and T. Kobori, "A 335 Mb/s 3.9 mm2 65 nm CMOS flexible MIMO detectiondecoding engine achieving 4G wireless data rates," in Proc. IEEE Int. ISSCC, Feb. 2012, pp. 216-218.
2. S. Höppner, H. Eisenreich, S. Henker, D. Walter, G. Ellguth, and R. Schüffny, "A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 3, pp. 566-570, Mar. 2013.
3. S. Höppner, C. Shao, H. Eisenreich, G. Ellguth, M. Ander, and R. Schüffny, "A power management architecture for fast per-core DVFS in heterogeneous MPSoCs," in Proc. IEEE ISCAS, May 2012, pp. 261-264.
4. L. Xiu, "A flying-adder on-chip frequency generator for complex SoC environment," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 12, pp. 1067-1071, Dec. 2007.
5. S. Höppner, S. Henker, H. Eisenreich, and R. Schüffny, "An open-loop clock generator for fast frequency scaling in 65 nm CMOS technology," in Proc. 18th Int. Conf. MIXDES, Jun. 2011, pp. 264-269.
6. H. Eisenreich, C. Mayr, S. Henker, M. Wickert, and R. Schüffny, "A novel ADPLL design using successive approximation frequency control," Microelectron. J., vol. 40, no. 11, pp. 1613-1622, Nov. 2009.
7. C.-T. Wu, W.-C. Shen, W. Wang, and A.-Y. Wu, "A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 6, pp. 430-434, Jun. 2010.
8. W. Jiang, A. Tavakol, P. Effendrik, M. van de Gevel, F. Verwaal, and R. B. Staszewski, "Design of ADPLL system for WiMAX applications in 40-nm CMOS," in Proc. 19th IEEE ICECS, Dec. 2012, pp. 73-76.
9. N. Da Dalt, "A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 1, pp. 21-31, Jan. 2005. (Pubitemid 40173701)
10. R. B. Staszewski and P. T. Balsara, "All-digital PLL with ultra fast settling," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 2, pp. 181-185, Feb. 2007. (Pubitemid 46477686)
11. Y. Li, C. Ornelas, H. S. Kim, H. Lakdawala, A. Ravi, and K. Soumyanath, "A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22 nm high-k tri-gate LP CMOS," in Proc. IEEE ISSCC, Feb. 2012, pp. 70-72.
12. N. August, H. jin Lee, M. Vandepas, and R. Parker, "A TDC-less ADPLL with 200-to-3200 MHz range and 3mW power dissipation for mobile SoC clocking in 22 nm CMOS," in Proc. IEEE ISSCC Digest Tech. Papers, Feb. 2012, pp. 246-248.
13. A. Rylyakov, J. Tierno, G. English, M. Sperling, and D. Friedman, "A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45 nm SOI," in Proc. IEEE CICC, Sep. 2008, pp. 431-434.