A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 246-247

  August, Nathaniel ^a   Lee, Hyung Jin ^a   Vandepas, Martin ^a   Parker, Rachael ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BATTERY LIFE; CLOCKING SYSTEMS; DIGITAL LOGIC; FLEXIBLE BANDWIDTH; LOCK TIME; LOW AREA; LOW POWER; MANUFACTURING PROCESS; PERIOD JITTER; SOC DESIGNS; WIDE FREQUENCY RANGE;

CLOCKS;

EID: 84860687639     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176995     Document Type: Conference Paper

References (6)

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2. A. Rylyakov, et al., "Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications," ISSCC Dig. Tech. Papers, pp. 94-95, 2009.
3. N. Da Dalt, "Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation," IEEE Trans. on Circuits and Systems-I, pp. 3663-3675, vol. 55, no. 11, 2008.
4. M.S.-W. Chen, et al., "A calibration-free 800MHz fractional-N digital PLL with embedded TDC," ISSCC Dig. Tech. Papers, pp. 472-473, 2010.
5. W. Yin, "A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery,", " ISSCC Dig. Tech. Papers, pp. 440-442, 2011.
6. J.A. Tierno, et al., "A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI," IEEE J. Solid-State Circuits, vol. 43, no., 1, pp. 42-51, 2008.