Design of ADPLL system for WiMAX applications in 40-nm CMOS

2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

Volumn , Issue , 2012, Pages 73-76

  Jiang, Wenlong ^a,c   Tavakol, Armin ^a   Effendrik, Popong ^a   Van De Gevel, Marcel ^b   Verwaal, Frank ^b   Staszewski, R Bogdan ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b Catena Radio Design   (Netherlands)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALL DIGITAL PHASE LOCKED LOOP; DIGITALLY CONTROLLED OSCILLATORS; DUAL BAND; FREQUENCY PLANNING; FREQUENCY RESOLUTIONS; GATE LEVELS; SETTLING TIME; TIME TO DIGITAL CONVERTERS; VERILOG-AMS;

FREQUENCY CONVERTERS; FREQUENCY SYNTHESIZERS;

WIMAX;

EID: 84874590626     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2012.6463568     Document Type: Conference Paper

References (5)

1. R. Staszewski and P. Balsara, All-digital frequency synthesizer in deepsubmicron CMOS. Wiley Online Library, 2006.
2. A. Tavakol, "Digitally Controlled Oscillator for WiMAX in 40 nm," Master's thesis, Delft University of Technology, 2012.
3. P. Effendrik, W. Jiang, M. van de Gevel, F. Verwaal, and R. Staszewski, "Time-to-digital converter (tdc) for wimax adpll in 40-nm cmos," in Circuit Theory and Design (ECCTD), 2011 20th European Conference on. IEEE, 2011, pp. 365-368.
4. R. Staszewski, S. Vemulapalli, and K. Waheed, "An all-digital offset PLL architecture," in Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE. IEEE, 2010, pp. 17-20.
5. K. Waheed, M. Sheba, R. Staszewski, F. Dulger, and S. Vamvakos, "Spurious free time-to-digital conversion in an ADPLL using short dithering sequences," in Custom Integrated Circuits Conference (CICC), 2010 IEEE. IEEE, 2010, pp. 1-4.