A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 70-71

  Li, Y William ^a   Ornelas, Carlos ^a   Kim, Hyung Seok ^a   Lakdawala, Hasnain ^a   Ravi, Ashoke ^a   Soumyanath, Krishnamurthy ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG PLL; BATTERY LIFE; CLOCK DOMAINS; CLOCK GENERATION; CLOCK GENERATION UNITS; CLOCK GENERATOR; CLOCK SIGNAL; CLOCK SKEWS; DIFFERENT FREQUENCY; DIGITAL CLOCKS; DIGITAL DOMAIN; FRACTIONAL-N; FREQUENCY ACCURACY; FREQUENCY RESOLUTIONS; FUNCTIONAL UNITS; GENERATION REQUIREMENTS; I/O INTERFACES; INTEGER-N; LOCALIZED DYNAMICS; LOCK TIME; LOOP BANDWIDTH; LOOP DYNAMICS; LOOP FILTER; MODULATION PATTERNS; MODULE INTERFACES; MULTIPLE REFERENCES; OFF-CHIP COMPONENTS; POWER MANAGEMENT UNIT; PROCESS SCALING; REFERENCE CLOCK; REFERENCE FREQUENCY; SKEW CORRECTIONS; SLEEP MODE; SPREAD SPECTRUM CLOCKING; TRANSISTOR LEAKAGE; TRIGATE; WIRELESS TRANSCEIVER;

BANDWIDTH; ENERGY MANAGEMENT;

ELECTRIC CLOCKS;

EID: 84860690736     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176934     Document Type: Conference Paper

References (3)

1. A. Ravi, et al., "A 9.2-12GHz, 90nm Digital Fractional-N Synthesizer with Stochastic TDC Calibration and -35/-41dBc Integrated Phase Noise in the 5/2.5GHz Bands," IEEE Symp. VLSI Circuits, pp. 143-144, 2010.
2. N. A. Kurd, et al., "Next Generation Intel Core Micro-Architecture (Nehelam) Clocking," J. of Solid-State Circuits, vol. 44, no. 4, pp. 1121-1129, 2009.
3. P. Madoglio, et al., "A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell design with Time-Interleaving, " J. of Solid-State Circuits, vol. 45, no.7, pp. 1410-1420, 2010.