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Volumn 55, Issue , 2012, Pages 434-435

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

Author keywords

[No Author keywords available]

Indexed keywords

BIOMEDICAL APPLICATIONS; CELL CURRENT; CURRENT-MODE SENSE AMPLIFIER; CURRENT-MODE SENSING; DATA STORAGE; LOW POWER; LOW-VOLTAGE; NON-VOLATILE MEMORIES; ON CHIPS; OUTPUT VOLTAGES; READ SPEED; RESISTIVE RAMS; SENSING MARGIN; WRITE OPERATIONS;

EID: 84860672719     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177079     Document Type: Conference Paper
Times cited : (84)

References (7)
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  • 2
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    • Conte, A.1
  • 3
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    • Design of a sense circuit for low-voltage Flash memories
    • April
    • T. Tanzawa, et al., "Design of a sense circuit for low-voltage Flash memories,"IEEE JSSC, pp. 877-883, April 2005
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    • Tanzawa, T.1
  • 4
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    • A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random access time and 160ns MLC-access capability
    • Feb
    • S.-S. Sheu, et al., "A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random access time and 160ns MLC-access capability," ISSCC, pp. 200-201, Feb 2011.
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    • Feb
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  • 6
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  • 7
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    • High density and ultra small cell size of contact ReRAM in 90nm CMOS logic technology and circuits
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.