A disturbance-free read scheme and a compact stochastic-spin-dynamics-based MTJ circuit model for Gb-scale SPRAM

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Ono, K ^a   Kawahara, T ^a   Takemura, R ^a   Miura, K ^a,b   Yamamoto, H ^a,b   Yamanouchi, M ^a   Hayakawa, J ^a   Ito, K ^a   Takahashi, H ^a   Ikeda, S ^b   Hasegawa, H ^a,b   Matsuoka, H ^a   Ohno, H ^b  

^a HITACHI LTD   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT MODELS; ELECTRICAL BIAS; EXPERIMENTAL MEASUREMENTS; FINITE TEMPERATURES; ON CHIP MEASUREMENTS; SPIN TRANSFER TORQUE; STOCHASTIC PROCESS; SWITCHING BEHAVIORS; SWITCHING PROBABILITY;

CIRCUIT SIMULATION; CIRCUIT THEORY; ELECTRON DEVICES; MAGNETIC DEVICES; RANDOM PROCESSES; STOCHASTIC MODELS; STOCHASTIC SYSTEMS;

SPIN DYNAMICS;

EID: 77952348902     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424382     Document Type: Conference Paper

References (5)

1. T. Kawahara, et al., JSSC 43, 2008, p. 109.
2. Z. Li, et al., Phys. Rev. B 69, 2004, p. 134416.
3. M. Madec, et al., NEWCAS-TAISA 2008, p. 229.
4. K. Ono, et al., VLSI Tech. Dig., 2009, p. 228.
5. R. Takemura, et al., VLSI Circuit. Dig., 2009, p. 84.