Scalability and design-space analysis of a 1T-1MTJ memory cell

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Volumn , Issue , 2011, Pages 32-36

  Dorrance, Richard ^a   Ren, Fengbo ^a   Toriyama, Yuta ^a   Amin, Amr ^a   Ken Yang, C K ^a   Marković, Dejan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Design Space; Magnetic Tunnel Junction; STT RAM; Variability

Indexed keywords

CRITICAL SWITCHING CURRENT; DESIGN POINTS; DESIGN SPACES; FEASIBILITY REGION; MAGNETIC TUNNEL JUNCTION; MEMORY CELL; MEMORY PERFORMANCE; STT-RAM; TARGET SPECIFICATIONS; TECHNOLOGY NODES; VARIABILITY;

DESIGN; MEMORY ARCHITECTURE; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; RANDOM ACCESS STORAGE; TUNNEL JUNCTIONS;

MAGNETIC DEVICES;

EID: 79961188860     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2011.5941480     Document Type: Conference Paper

References (10)

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