A yield-aware modeling methodology for nano-scaled SRAM designs

2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2005, Pages 33-36

  Grossar, Evelyn ^a,b   Croon, Jeroen ^a,c   Stucchi, Michele ^a   Dehaene, Wim ^b   Maex, Karen ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; NANOTECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

MEMORY ARRAYS; PARAMETRIC VARIATIONS;

INTEGRATED CIRCUIT LAYOUT;

EID: 25844434308     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2005.1502584     Document Type: Conference Paper

References (16)

1. S.Narendra, et al.,"Leakage issues in IC design: Trends, estimation and avoidance," Tutorial ICCAD 2003
2. R.Preston, et al., "Managing variability on sub-100nm designs," Microprocessor Circuit Forum at IEEE Solid State Circuit Conf., San Francisco CA, February 2004
3. B.Cheng et al. "The impact of random doping effects on CMOS SRAM cell, Proc. ESSCIRC, 2004, p219-222
4. Yu Cao et al. "Yield Optimization with Energy-Delay Con straints in Low-Power Digital Circuits,"Proc. Electron Devices and Solid-State Circuits, 2003, pp. 285-288
5. Rao R.R. et al.,"Parametric Yield Estimation Considering Leakage Variability."Proc. DAC 2004, pp. 442-447
6. S.Nassif,"Delay Variability:, Sources, Impacts and Trends,"Proc.ISSCC 2000, pp. 368-369
7. A.Srivastava et al. "Statistical Optimization of Leakage Power Considering Process Variations using Dual-Vth and Sizing," Proc. DAC 2004, pp. 773-778
8. A. Alvandpour et al.,"Bitline Leakage Equalization for Sub-100nm Caches,"Proc. ESSCIRC2003, pp. 401-404
9. S.Mukhopadhyay, et al.,"Modeling and Estimation of Failure Probability due to Parametric Variations in Nano-scale SRAMs for Yield Enhancement,"2004 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 64-67
10. J.M.Rabaey, et al.,"Digital Integrated Circuits: A Design Perspective,"2003,ISBN 0130909963
11. S.R. Nassif,"Design for Variability in DSM technologies," ISQED, 2000, pp. 451-454
12. A.Papoulis,"Probability, Random Variables and Stochastic Process,"New York: McGraw-Hill 1991, ISBN 0070484775
13. K.Roy, et al.,"Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits.Proc. of IEEE, VOL. 91, NO.2, pp.305-327, February 2003
14. M.Romeo et al.,"Broad distribution effects in sums of lognormal random variables,"Eur.Phys.J.B32,pp 513-525 (2003)
15. R.Rao et al., "Statistical Analysis of Subthreshold Leakage Current for VLSI Circuits,"IEEE Trans. on VLSI systems", Vol12, no.2, pp. 131-139, February 2004
16. M.J.M Pelgrom et al.,"Matching Properties of MOS Transistors,"IEEE JSSC, vol24, no.5, pp. 1433-1439, october 1989