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Volumn , Issue , 2002, Pages 509-518

Experimental evaluation of scan tests for bridges

Author keywords

[No Author keywords available]

Indexed keywords

BRIDGES; COMPUTER SIMULATION; FAILURE ANALYSIS; MATHEMATICAL MODELS;

EID: 0036443088     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2002.1041801     Document Type: Article
Times cited : (28)

References (16)
  • 1
    • 0024124693 scopus 로고    scopus 로고
    • Extraction and simulation of realistic faults using inductive fault analysis
    • J. F. Ferguson and J. P. Shen, "Extraction and Simulation of Realistic Faults using Inductive Fault Analysis," IEEE International Test Conference, 1988, pp. 475-484.
    • IEEE International Test Conference, 1988 , pp. 475-484
    • Ferguson, J.F.1    Shen, J.P.2
  • 3
    • 0034482034 scopus 로고    scopus 로고
    • A scalable and efficient methodology to extract two node bridges from large industrial circuits
    • S. T. Zachariah and S. Chakravarty, "A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits," IEEE International Test Conference, 2000.
    • IEEE International Test Conference, 2000
    • Zachariah, S.T.1    Chakravarty, S.2
  • 6
  • 8
    • 0022089113 scopus 로고
    • A practical approach to fault simulation and test generation for bridging faults
    • July
    • M. Abramovici and M. Breuer, "A Practical Approach to Fault Simulation and Test Generation for Bridging Faults," IEEE Transactions on Computers, C-34 (7): 658-663, July 1985.
    • (1985) IEEE Transactions on Computers , vol.C-34 , Issue.7 , pp. 658-663
    • Abramovici, M.1    Breuer, M.2
  • 10
    • 0027883887 scopus 로고
    • Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds
    • Peter C. Maxwell and Robert C. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds," IEEE International Test Conference, pp. 63-72, 1993.
    • (1993) IEEE International Test Conference , pp. 63-72
    • Maxwell, P.C.1    Aitken, R.C.2
  • 11
    • 0031337485 scopus 로고    scopus 로고
    • BART: A bridging fault test generator for sequential circuits
    • Nov
    • J.P. Cusey and J. H. Patel, "BART: A Bridging Fault Test Generator for Sequential Circuits," IEEE International Test Conference, pp. 838-847, Nov. 1997.
    • (1997) IEEE International Test Conference , pp. 838-847
    • Cusey, J.P.1    Patel, J.H.2
  • 12
    • 0002614343 scopus 로고
    • Testing CMOS logic gates for realistic shorts
    • B. Chess, et al., "Testing CMOS Logic Gates for Realistic Shorts," IEEE International Test Conference, pp. 395-402, 1994.
    • (1994) IEEE International Test Conference , pp. 395-402
    • Chess, B.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.