-
1
-
-
0024124693
-
Extraction and simulation of realistic faults using inductive fault analysis
-
J. F. Ferguson and J. P. Shen, "Extraction and Simulation of Realistic Faults using Inductive Fault Analysis," IEEE International Test Conference, 1988, pp. 475-484.
-
IEEE International Test Conference, 1988
, pp. 475-484
-
-
Ferguson, J.F.1
Shen, J.P.2
-
5
-
-
84948443065
-
Layout analysis to extract open nets caused by systematic failure mechanisms
-
to appear
-
S. Chakravarty, K Komeyli, E. W. Savage, M. J. Carruthers, B. T. Statsny, S. T. Zachariah, "Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms", IEEE VLSI Test Symposium, 2002, to appear.
-
IEEE VLSI Test Symposium, 2002
-
-
Chakravarty, S.1
Komeyli, K.2
Savage, E.W.3
Carruthers, M.J.4
Statsny, B.T.5
Zachariah, S.T.6
-
7
-
-
0033300347
-
On detecting bridges causing timing failures
-
S. Chakravarty, S. Mandava and S. Kundu, "On Detecting Bridges Causing Timing Failures," IEEE International Conference on Computer Design, 1999, pp. 400-406.
-
IEEE International Conference on Computer Design, 1999
, pp. 400-406
-
-
Chakravarty, S.1
Mandava, S.2
Kundu, S.3
-
8
-
-
0022089113
-
A practical approach to fault simulation and test generation for bridging faults
-
July
-
M. Abramovici and M. Breuer, "A Practical Approach to Fault Simulation and Test Generation for Bridging Faults," IEEE Transactions on Computers, C-34 (7): 658-663, July 1985.
-
(1985)
IEEE Transactions on Computers
, vol.C-34
, Issue.7
, pp. 658-663
-
-
Abramovici, M.1
Breuer, M.2
-
10
-
-
0027883887
-
Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds
-
Peter C. Maxwell and Robert C. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds," IEEE International Test Conference, pp. 63-72, 1993.
-
(1993)
IEEE International Test Conference
, pp. 63-72
-
-
Maxwell, P.C.1
Aitken, R.C.2
-
11
-
-
0031337485
-
BART: A bridging fault test generator for sequential circuits
-
Nov
-
J.P. Cusey and J. H. Patel, "BART: A Bridging Fault Test Generator for Sequential Circuits," IEEE International Test Conference, pp. 838-847, Nov. 1997.
-
(1997)
IEEE International Test Conference
, pp. 838-847
-
-
Cusey, J.P.1
Patel, J.H.2
-
12
-
-
0002614343
-
Testing CMOS logic gates for realistic shorts
-
B. Chess, et al., "Testing CMOS Logic Gates for Realistic Shorts," IEEE International Test Conference, pp. 395-402, 1994.
-
(1994)
IEEE International Test Conference
, pp. 395-402
-
-
Chess, B.1
-
15
-
-
0035681196
-
A study of bridging defect probabilities on a pentium™ 4 CPU
-
V. Krishnamurthy, A. B. Ma and P. Vishakantiah, "A Study of Bridging Defect Probabilities on a Pentium™ 4 CPU," IEEE International Test Symposium, 2001, pp. 688-695.
-
IEEE International Test Symposium, 2001
, pp. 688-695
-
-
Krishnamurthy, V.1
Ma, A.B.2
Vishakantiah, P.3
-
16
-
-
0033354540
-
A comparison of bridging fault simulation methods
-
S. Ma, I. Shaik and R. Scott Fetherston, "A Comparison of Bridging Fault Simulation Methods," IEEE International Test Conference, 1999, pp. 587-595.
-
IEEE International Test Conference, 1999
, pp. 587-595
-
-
Ma, S.1
Shaik, I.2
Fetherston, R.S.3
|