Multi-layer adaptive power management architecture for TSV 3DIC applications

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2013, Pages 1179-1185

  Chang, Ming Hung ^a,b   Hsieh, Wei Chih ^a   Wu, Pei Chen ^a   Chuang, Ching Te ^a   Chen, Kuan Neng ^a   Wang, Chen Chao ^b   Ting, Chun Yen ^b   Chen, Kua Hua ^b   Chiu, Chi Tsung ^b   Tong, Ho Ming ^b   Hwang, Wei ^a,c  

^a Department of Electronics Engineering and Institute of Electronics ^*  (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE POWER MANAGEMENT; DECOUPLING CAPACITOR; DISTRIBUTED POWER; HETEROGENEOUS INTEGRATION; MULTI-THRESHOLD CMOS; POWER ARCHITECTURES; POWER EFFICIENCY; VOLTAGE STABILIZATION;

DC-DC CONVERTERS; ELECTRIC NETWORK ANALYSIS; ENERGY MANAGEMENT;

ELECTRIC POWER TRANSMISSION;

EID: 84883342131     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2013.6575724     Document Type: Conference Paper

References (17)

1. X. Wu, et al., "SI and EMI Impact of AC Coupling Capacitors on 25Gbps and Beyond Systems," Designcon 2013, Santa Clara, CA Jan. 2013
2. P. Amleshi, et al., "Interconnect Design Optimization and Characterization for Advanced High Speed Backplane Channel Links," Designcon 2009, Santa Clara, CA, Jan. 2009
3. T. Spencer, R. Saha, J. Chen, R. Bashirullah and P. Kohl, " Air Cavidty Transmission Lines for Off-chip Interconnects Characterized to 40GHz, IEEE Trans-CPMT, Vol. 2, No.3, March 2012, pp. 367-374
4. R. Dame, G. Blando, I. Novak, J. Miller, K. Hinckley, "Via, Structural Details and their Effect on System Performance", Desigcon 2012, Santa Clara,CA, Jan. 2012
5. J. Izadian, J. Ferry, J. McAllister, "Novel Transmission Line for 40GHz PCB Applications", Designcon 2011, Santa Clara, CA, Jan. 2011
6. Impact connector routing guide, Molex Inc., available at http://www.molex.com/pdm-docs/as/AS-76060-990.pdf
7. G. Schrom, P. Hazucha, J.-H. Hahn, V. Kursun, D. Gardner, S. Narendra, T. Karnik, and V. De, "Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation," in Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2004, pp. 263-268.
8. P. Jain, T.-H. Kim, J. Keane, and C. H. Kim, "A multi-story power delivery technique for 3D integrated circtuis," in Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2008, pp. 57-62.
9. T.-H. Lin, P.-T. Huang, and W. Hwang, "Power noise suppression technique using active decoupling capacitor for TSV 3D integration," in IEEE Int. System-on-Chip Conf. (SOCC), Sep. 2010, pp. 209-212.
10. P.-J. Yang, P.-T. Huang, and W. Hwang, "Substrate noise suppression technique for power integrity of TSV 3D integration," in IEEE Int. Symp. Circuits Syst. (ISCAS), May 2012, pp. 3274-3277.
11. S.-L. Chen and M.-D. Ker, "A new Schmitt trigger circuit in a 0.13-?m 1/2.5-V CMOS process to receive 3.3-V input signals," IEEE Trans. Circuits Syst. II, vol. 52, no. 7, pp. 361-365, Jul. 2005.
12. J. Sun, D. Giuliano, S. Devarajan, J.-Q. Lu, T. P. Chow, and R. J. Gutmann, "Fully monolithic cellular buck converter design for 3-D power delivery," IEEE Trans. VLSI Syst., vol. 17, no. 3, pp. 447-451, Mar. 2009.
13. Y. K. Ramadass and A. P. Chandrakasan, "Voltage scalable switched capacitor DC-DC converter for ultra-low-power on-chip applications," in IEEE Power Electronics Specialist Conf. (PESC), 2007, pp. 2353-2359.
14. J. Kwong, Y. K. Ramadass, and A. P. Chandrakasan, "A 65nm Sub-Vt microcontroller with integrated SRAM and switched capacitor DC-DC converter," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 115-126, Jan. 2009.
15. W.-C. Hsieh and W. Hwang, "All digital linear voltage regultor for super-to near-threshold operation," IEEE Trans. on VLSI Syst., vol. 20, no. 6, pp. 989-1001, 2012.
16. W.-C. Hsieh and W. Hwang, "Adaptive power control technique on power-gated circuitries," IEEE Trans. on VLSI Syst., vol. 19, no. 7, pp. 1167-1180, 2011
17. M.-H. Chang, S.-Y. Lin, and W. Hwang, "A 0.4V 520nW 990?m2 fully integrated frequency-domain smart temperature sensor in 65nm CMOS," ASP J. of Low Power Electronics, vol. 8, no. 1, pp. 63-72, Feb. 2012.