Fully monolithic cellular buck converter design for 3-D power delivery

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 3, 2009, Pages 447-451

  Sun, Jian ^a   Giuliano, David ^a,c   Devarajan, Siddharth ^a,b   Lu, Jian Qiang ^a   Chow, T Paul ^a   Gutmann, Ronald J ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b Linear Technology Inc

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

3 D integration; Dc to dc converters; Monolithic power conversion; Power delivery; Power management; Voltage regulator

Indexed keywords

BICMOS TECHNOLOGY; DESIGN; DYNAMIC RESPONSE; ELECTRIC POTENTIAL; ELECTRIC POWER MEASUREMENT; ENERGY MANAGEMENT; POWER CONVERTERS; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; VOLTAGE CONTROL; VOLTAGE STABILIZING CIRCUITS;

3-D INTEGRATION; DC-TO-DC CONVERTERS; MONOLITHIC POWER CONVERSION; POWER DELIVERY; POWER MANAGEMENT;

ELECTRIC POWER TRANSMISSION;

EID: 63149124720     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2005312     Document Type: Article

References (13)

1. ITRS, "International Technology Roadmap for Semiconductors (ITRS)," 2005.
2. G. Schrom, P. Hazucha, J. Hahn, V. Kursun, D. Gardner, S. Narendra, T. Karnik, and V. De, "Feasibility of monolithic and 3D-stacked dc-dc converters for microprocessor in 90 nm technology generation," in Proc. ISLPED, 2004, pp. 263-268.
3. J. A. Harrison and E. R. Stanford, "Z-axis processor power delivery system," U.S. Patent 6 523 253, Feb. 25, 2003.
4. S. Chandrasekaran, J. Sun, and V. Mehrotra, "Vertically packaged switched-mode power converter," U.S. Patent 7 012 414, Mar. 14, 2006.
5. J. Sun, J. Q. Lu, D. Giuliano, T. P. Chow, and R. J. Gutmann, "3D power delivery for microprocessors and high-performance ASICs," in Proc. IEEE Appl. Power Electron. Conf., 2007, pp. 127-133.
6. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, "Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 3, pp. 514-522, Mar. 2003.
7. M. Crawford and S. X. Wang, "Effect of patterned magnetic shields on high-frequency integrated inductors," IEEE Trans. Magn., vol. 40, no. 7, pp. 2017-2019, Jul. 2004.
8. G. Schrom, P. Hazucha, J. Hahn, D. Gardner, B. Bloechel, G. Dermer, S. Narendra, T. Karnik, and V. De, "A 480-MHz, multi-phase interleaved buck dc-dc converter with hysteretic control," in Proc. Rec. IEEE Power Electron. Specialists Conf., pp. 4702-4707.
9. C. F. Lee and P. K. T. Mok, "A monolithic current-mode CMOS dc-dc converter with on-chip current-sensing technique," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 3-14, Jan. 2004.
10. J. Sun, "Control design considerations for voltage regulator modules," in Proc. IEEE INTELEC, 2003, pp. 84-91.
11. D. Guiliano, "Monolithic DC-DC converters for 3D enabled power delivery," M.S. thesis, Dept. ECSE, Rensselaer Polytech. Inst., 2006.
12. Intel, Santa Clara, CA, "Intel core duo processor and Intel core solo processor on 65 nm process," Doc. 309221-001, 2006.
13. S. Jayawant and J. Sun, "Double-integral Fourier analysis of interleaved pulse-width modulation," in Proc. IEEE COMPEL Workshop, 2006, pp. 34-39.