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Volumn , Issue , 2012, Pages 259-263

A novel high-performance fault-tolerant ICAP controller

Author keywords

Dynamic Partial Reconfiguration; FPGA; ICAP; TMR

Indexed keywords

DYNAMIC PARTIAL RECONFIGURATION; FAULT-TOLERANT; FPGA CHIPS; ICAP; INTERNAL CONFIGURATION ACCESS PORTS; IP CORE; TMR; TRIPLE MODULAR REDUNDANCY;

EID: 84866637152     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHS.2012.6268660     Document Type: Conference Paper
Times cited : (21)

References (14)
  • 3
    • 0141837018 scopus 로고    scopus 로고
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    • C. Constantinescu, "Trends and challenges in VLSI circuit reliability," IEEE Micro, vol. 23, no. 4, pp. 4-19, 2003.
    • (2003) IEEE Micro , vol.23 , Issue.4 , pp. 4-19
    • Constantinescu, C.1
  • 4
    • 79951748667 scopus 로고    scopus 로고
    • Xilinx, Xilinx DS586
    • Xilinx, "LogiCORE IP XPS HWICAP," Xilinx DS586 2010.
    • (2010) LogiCORE IP XPS HWICAP
  • 6
    • 70449922693 scopus 로고    scopus 로고
    • Run-time partial reconfiguration speed investigation and architectural design space exploration
    • Giessen, Germany
    • M. Liuyz, W. Kuehnz, Z. Luy, and A. Jantschy, "Run-time partial reconfiguration speed investigation and architectural design space exploration," FPL 2009, Giessen, Germany.
    • (2009) FPL
    • Liuyz, M.1    Kuehnz, W.2    Luy, Z.3    Jantschy, A.4
  • 7
    • 33749343591 scopus 로고    scopus 로고
    • Methods for runtime failure recognition and recovery in dynamic and partial reconfigurable systems based on Virtex II Pro FPGAs
    • Karlsruhe, Germany
    • K. Paulsson, M. Huebner, M. Jung, and J. Becker, "Methods for runtime failure recognition and recovery in dynamic and partial reconfigurable systems based on Virtex II Pro FPGAs," ISVLSI 2006, Karlsruhe, Germany.
    • (2006) ISVLSI
    • Paulsson, K.1    Huebner, M.2    Jung, M.3    Becker, J.4
  • 12


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.