A design methodology to implement memory accesses in high-level synthesis

Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11

Volumn , Issue , 2011, Pages 49-58

  Pilato, Christian ^a   Ferrandi, Fabrizio ^a   Sciuto, Donatella ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

High level synthesis; Memory optimization

Indexed keywords

BEHAVIORAL SPECIFICATION; C LANGUAGE; COMPILE TIME; DESIGN CONSTRAINTS; DESIGN METHODOLOGY; FUNCTION CALLS; HARDWARE ACCELERATORS; HIGH LEVEL SYNTHESIS; MEMORY ACCESS; MEMORY ADDRESS; MEMORY OPTIMIZATION; MEMORY SYNTHESIS; POINTER ARITHMETIC;

C (PROGRAMMING LANGUAGE); CODES (SYMBOLS); DATA FLOW ANALYSIS; DESIGN; SPECIFICATIONS;

EMBEDDED SYSTEMS;

EID: 81355136059     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2039370.2039381     Document Type: Conference Paper

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