메뉴 건너뛰기




Volumn II, Issue , 2005, Pages 876-881

A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ENERGY EFFICIENCY; OPTIMIZATION; SIGNAL PROCESSING; VIRTUAL REALITY; XML;

EID: 33646898466     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.21     Document Type: Conference Paper
Times cited : (84)

References (27)
  • 1
    • 2042458649 scopus 로고    scopus 로고
    • A survey of processors with explicit multithreading
    • March
    • T. Lingerer, B. Robic, J. Silc. A Survey of Processors with Explicit Multithreading. ACM Computing Surveys, 35(1):29-63, March 2003.
    • (2003) ACM Computing Surveys , vol.35 , Issue.1 , pp. 29-63
    • Lingerer, T.1    Robic, B.2    Silc, J.3
  • 16
    • 0036857007 scopus 로고    scopus 로고
    • Stepnp: A system-level exploration platform for network processors
    • Nov-Dec
    • E. Bensoudane P.G. Paulin, C. Pilkington. Stepnp: A system-level exploration platform for network processors. IEEE Design & Test of Computers, 19(6): 17-26, Nov-Dec 2002.
    • (2002) IEEE Design & Test of Computers , vol.19 , Issue.6 , pp. 17-26
    • Bensoudane, E.1    Paulin, P.G.2    Pilkington, C.3
  • 20
    • 0036858279 scopus 로고    scopus 로고
    • A hardware-software real-time operating system framework for SoC's
    • Nov/Dec
    • V. J. Mooney, D. M. Blough. A Hardware-Software Real-Time Operating System Framework for SoC's. IEEE Design & Test of Computers, 19(6):44-51. Nov/Dec 2002.
    • (2002) IEEE Design & Test of Computers , vol.19 , Issue.6 , pp. 44-51
    • Mooney, V.J.1    Blough, D.M.2
  • 25
    • 4444268368 scopus 로고    scopus 로고
    • A modular simulation framework for architectural exploration of on-chip interconnection networks
    • October
    • T. Kogel, M. Doerper, A. Wieferink, R. Leupers, G. Ascheid, H. Meyr, and S. Goossens. A Modular Simulation Framework for Architectural Exploration of On-Chip Interconnection Networks. In CODES+ISSS, October 2003.
    • (2003) CODES+ISSS
    • Kogel, T.1    Doerper, M.2    Wieferink, A.3    Leupers, R.4    Ascheid, G.5    Meyr, H.6    Goossens, S.7
  • 27
    • 84871489058 scopus 로고    scopus 로고
    • Intel Network Processors. http://developer.intel.com/design/network/ products/npfamily/.
    • Intel Network Processors


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.