Low-temperature sintering of a nanosilver paste for attaching large-area power chips

Proceedings - International Symposium on Advanced Packaging Materials

Volumn , Issue , 2013, Pages 192-202

  Xiao, Kewei ^a   Luo, Susan ^b   Ngo, Khai ^c   Lu, G Q ^a,c  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

^b NBE Technologies LLC   (United States)

^c Virginia Polytechnic Institute and State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FRACTIONAL FACTORIAL DESIGNS; HIGHER JUNCTION TEMPERATURES; LOW-TEMPERATURE SINTERING; POWER ELECTRONICS DEVICES; PROCESSING PARAMETERS; SHRINKAGE BEHAVIOR; SINTERING TEMPERATURES; SOLVENT EVAPORATION;

CHIP SCALE PACKAGES; DESIGN OF EXPERIMENTS; DIES; OPTICAL SYSTEMS; PACKAGING; PACKAGING MATERIALS; POWER ELECTRONICS; SILVER; TEMPERATURE;

SINTERING;

EID: 84878867399     PISSN: 15505723     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISAPM.2013.6510403     Document Type: Conference Paper

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