MOrpheus: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems

Transactions on Embedded Computing Systems

Volumn 12, Issue 3, 2013, Pages

  Voros, Nikolaos S ^a   Hubner, Michael ^b   Becker, Jurgen ^b   Kuhnle, Matthias ^b   Thomaitiv, Florian ^b   Grasset, Arnaud ^c   Brelet, Paul ^c   Bonnot, Philippe ^c   Campi, Fabio ^d   Schuler, Eberhard ^e   Sahlbach, Henning ^f   Whitty, Sean ^f   Ernst, Rolf ^f   Billich, Enrico ^g   Tischendorf, Claudia ^g   Heinkel, Ulrich ^g   Ieromnimon, Frank ^h   Kritharidis, Dimitrios ^h   Schneider, Axel ⁱ   Knaeblein, Joachim ⁱ   Putzke Roming, Wolfram ^j   more..

^a TECHNOLOGICAL EDUCATIONAL INSTITUTE OF PATRAS   (Greece)

^b UNIVERSITY OF KARLSRUHE   (Germany)

^c THALES RESEARCH AND TECHNOLOGY   (France)

^d STMICROELECTRONICS   (Italy)

^e PACT XPP Technologies   (United States)

^f TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

^g CHEMNITZ UNIVERSITY OF TECHNOLOGY   (Germany)

^h INTRACOM TELECOM   (Greece)

ⁱ NOKIA RESEARCH CENTER   (United States)

^j Deutsche Thomson OHG ^*  (Germany)

more..

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX APPLICATIONS; DESIGN FRAMEWORKS; HARDWARE ARCHITECTURE; HETEROGENEOUS CHARACTERISTIC; INNOVATIVE TECHNOLOGY; RECONFIGURABLE PLAT-FORMS; SYSTEM DESIGNERS; TECHNOLOGY PROVIDERS;

APPLICATION PROGRAMS;

DESIGN;

EID: 84878473875     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/2442116.2442120     Document Type: Article

References (46)

1. BELL, S., et al. 2008. TILE64 processor: A 64-core SoC with mesh interconnect. Intl. Conference on Solid-State Circuits (ISSCC). 88-89.
2. BERTIN, P., RONCIN, D., AND VUILLEMIN J. 1989. Introduction to Programmable Active Memories. Prentice Hall, 300-309.
3. BONNOT, P., LEMONNIER, F., EDELIN, G., GAILLAT, G., RUCH, O., AND GAUGET, P. 2008. Definition and SIMD implementation of a multi-processing architecture approach on FPGA. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE '08). 610-615.
4. CAMBONIE, J., GU'ERIN, S., KERYELL, R., LAGADEC, L., POTTIER, B., SENTIEYS, O.,WEBER, B., AND YAZDANI, S. 2004. Compiler and system techniques for soc distributed reconfigurable accelerators. In Proceedings of the 4th International Workshop on Synthesis, Architectures, Modeling and Simulation (SAMOS). 293-302.
5. CAMPI, F., DELEDDA, A., PIZZOTTI, M., CICCARELLI, L., MUCCI, C., LODI, A., VANZOLINI, L., AND VITKOVSKI, A. 2007. Dynamically adaptive DSP for heterogeneous reconfigurable platforms. Proceedings of the Design Automation and Test in Europe (DATE).
6. CAMPI, F., TOMA, M., LODI, A., CAPPELLI, A., CANEGALLO, R., AND GUERRIERI, R. 2003. A VLIW processor with reconfigurable instruction set for embedded applications. Proceedings of the International Solid State Circuits Conference.
7. CRITICALBLUE, 2005. Boosting software processing performance with coprocessor synthesis. White paper.
8. COPPOLA, M., LOCATELLI, R., MARUCCIA, G., PIERALISI, L., AND SCANDURRA, A. 2004. Spidergron: A novel on-chip communication network. Proceedings of the IEEE Symposium on System on Chip (SoC'09).
9. CAPPELLI, A., LODI, A.,MUCCI, C., TOMA, M., AND CAMPI, F. 2004. A dataflow control unit for C-to-configurable pipelines compilation flow. Proceedings of the 12th Annual Symposium on Field-Programmable Custom Computing Machines (FCCM). 332-333.
10. COMPTON, K. AND HAUCK, S. 2002. Reconfigurable computing: A survey of systems and software. ACM Computing Surveys 23, 2, 171-210.
11. DEHON, A. The density advantage of configurable computing. IEEE Computer.
12. DEHON, A., et al. 2006. Stream computations organized for reconfigurable execution. Microprocessors and microsystems 30, 6, 334-354, Special Issue on FPGAs.
13. DO CARMO, L., A., HEITHECKER, S., RUFFER, P., ERNST, R., RUCKERT, H., WISCHERMANN, G., GEBEL, K., FACH, R., HUNTHER,W., EICHNER, S., AND SCHELLER,G. 2006. A reconfigurable hardware/software platform for computation intensive high-resolution real-time digital film applications. In Proceedings of Design, Automation and Test in Europe (DATE). 194-199.
14. DUTTA, S., JENSEN, R., AND RIECKMANN, A. 2001. Viper: A multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Design & Test of Computers 16, 5, 21-31.
15. ESTRIN, G. 1960. Organization of computer systems-the fixed plus variable structure computer. Proceedings of Western Joint Computer Conference. 33-40.
16. EICHNER, S., SCHELLER, G., WESSELY, U., RUCKERT, H., AND HEDTKE, R. 2005. Motion compensated spatialtemporal reduction of film grain noise in the wavelet domain. In Proceedings of the SMPTE Technical Conference.
17. FARABOSCHI, BROWN, FISHER, DESOLI. 2000. Lx: A technology platform for customizable VLIW embedded processing. Proceedings of the 27th Annual International Symposium of Computer Architectures.
18. GOLDSTEIN, S. et al. 1999. PipeRench: A coprocessor for streaming multimedia acceleration. Proceedings of the 26th Int'l Symp. Computer Architecture (ISCA'99). 28-39.
19. HARTENSTEIN, R. 2001. A decade of reconfigurable computing: A visionary retrospective. Proceedings of the Design, Automation and Test in Europe (DATE '01). 642-649.
20. HARTENSTEIN, R. 2003. Rekonfigurable computing: Paradigmen-Wechsel ersch uttern die fundamente der informatik. Proceedings of the Anniversary Colloquium at Prof. Glesner's 60s Birthday.
21. HAUSER, WAWRZINEK. 1997. Garp: A MIPS processor with reconfigurable coprocessor. Proceedings of the Symposium on Field Programmable Custom Computing Machines.
22. KUEHNLE, M. et al. 2008. An interconnect strategy for a heterogeneous, reconfigurable SoC. IEEE Design & Test of Computers.
23. LE GALL D. AND TABATABAI, A. 1988. Sub-band coding of digital images using symmetric short kernel filters and arithmetic coding techniques. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP'88). 761-764.
24. LENORMAND, E. AND EDELIN, G. 2003. An industrial perspective: Pragmatic high-end signal processing environment at Thales. In Proceedings of the 3rd International Workshop on Synthesis, Architectures, Modeling and Simulation (SAMOS).
25. LINDHOLM, E., NICKOLLS, J., OBERMAN, S., AND MONTRYM, J. 2008. NVIDIA Tesla: A unified graphics and computing architecture. IEEE Micro 28, 2, 39-55.
26. MOSCU PANAINTE, E.,BERTELS, K., AND VASSILIADIS, S. 2004. The PowerPC Backend Molen Compiler. In Proceedings of 14th International Conference on Fleld-Programmable Logic and Applications (FPL). 434-443.
27. MOSCU PANAINTE, E., BERTELS, K., AND VASSILIADIS, S. 2005a. FPGA-area allocation for partial run-time reconfiguration. Proceedings of ProRISC. 415-420.
28. MOSCU PANAINTE, E., BERTELS, K., AND VASSILIADIS, S. 2005b. Instruction scheduling for dynamic hardware configurations. In Proceedings of Design, Automation and Test in Europe (DATE '05). 100-105.
29. MOSCU PANAINTE, E., BERTELS, K., AND VASSILIADIS, S. 2007. TheMOLENCompiler for reconfigurable processors. ACM Transactions in Embedded Computing Systems 6, 1.
30. MUCCI, C., CHIESA, C., LODI, A., TOMA, M., AND CAMPI, F. 2003. A C-based algorithm development flow for a reconfigurable processor architecture. In Proceedings of the International Symposium on Systems-on-Chip (SOC'03). 69-73.
31. NOMADIK. 2007. NOMADIK R: A mobile multimedia application processor platform. Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'07). 749-750.
32. OMAP. http://www.ti.com
33. PACT XPP Technologies. 2005. PACT Software Design System XPP-IIb (PSDS XPP-IIb)-Programming Tutorial. Version 3.2, November 2005.
34. RADUNOVIC, B. 1999. An overview of advances in reconfigurable computing systems. Proceedings of the 32nd Hawaii International Conference on System Science.
35. ROSSI, D., CAMPI, F., DELEDDA, A., SPOLZINO, S., AND PUCILLO, S. 2009. A heterogeneous digital signal processor implementation for dynamically reconfigurable computing. IEEE Custom Integrated Circuits Conference (CICC).
36. SAHLBACH, H.,PUTZKE-ROMING,W.,WHITTY, S. AND ERNST, R. 2009. Real-time digital film processing. In Dynamic System Reconfiguration in Heterogeneous Platforms-The MORPHEUS Approach. Lecture Notes in Electrical Engineering, vol. 40, Springer, 185-193.
37. SANZ, C., GARRIDO, M. J., AND MENESES, J. M. 1996. VLSI architecture for motion estimation using the blockmatching algorithm. In Proceedings of the EDTC. 310
38. SINGH, H. et al. 2000. MorphoSys: An integrated reconfigurable system for data-parallel and computationintensive applications. IEEE Trans. Computers 49, 5, 465-481.
39. THOMAS, A. AND BECKER, J. 2004. Dynamic adaptive routing techniques in multigrain dynamic reconfigurable hardware architectures. Proceedings of the Field-Programmable Logic and Its Applications (FPL'04).
40. TRUONG, D. N., CHENG, W. H.,MOHSENIN, T., ZHIYI, Y., JACOBSON, A. T., LANDGE, G.,MEEUWSEN, M. J.,WATNIK, C., TRAN, A. T., ZHIBIN, X., WORK, E. W., WEBB, J. W., MEJIA, P. V., AND BAAS, B. M. 2009. A 167-processor computational platform in 65 nm CMOS. IEEE Journal of Solid-State Circuits 44, 4, 1130-1144.
41. VASSILIADIS, S., WONG, S., GAYDADJIEV, G., BERTELS, K., KUZMANOV, G., AND PANAINTE, E. 2004. The MOLEN polymorphic processor. IEEE Trans. Comput. 53, 11, 1363-1375.
42. VORBACH, M. AND BECKER, J. 2003. Reconfigurable processor architectures for mobile phones. Proceedings of Parallel and Distributed Processing Symposium.
43. WHITTY, S. AND ERNST, R. 2008. A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture. In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS).
44. WHITTY, S., SAHLBACH, H., PUTZKE-ROMING, W., AND ERNST, R. 2009. Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture. In Proceedings of Design, Automation and Test in Europe (DATE).
45. WHITTY, S., SAHLBACH, H., HURLBURT, B., PUTZKE-ROMING, W., AND ERNST, R. 2010. Application-specific memory performance of a heterogeneous reconfigurable architecture. In Proceedings of Design, Automation and Test in Europe (DATE).
46. WOLF, M. E. AND LAM, M. S. 1991. A data locality optimizing algorithm. Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI'91).