A C-based algorithm development flow for a reconfigurable processor architecture

2003 International Symposium on System-on-Chip, SoC 2003 - Proceedings

Volumn , Issue , 2003, Pages 69-73

  Mucci, Claudio ^a   Chiesa, Carlo ^a   Lodi, Andrea ^a   Toma, Mario ^a   Campi, Fabio ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHM DEVELOPMENT; DATA FLOW GRAPHS; DSP ALGORITHM; ENERGY CONSUMPTION; EXECUTABLE CODES; LOW ENERGY CONSUMPTION; PROCESSOR CORES; PROGRAMMABLE HARDWARE; RECONFIGURABLE PROCESSORS; TEST-CHIP;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA FLOW ANALYSIS; DIGITAL SIGNAL PROCESSORS; EMBEDDED SYSTEMS; ENERGY UTILIZATION; HIGH LEVEL LANGUAGES; PROGRAMMABLE LOGIC CONTROLLERS; RECONFIGURABLE HARDWARE; REDUCED INSTRUCTION SET COMPUTING; SIGNAL PROCESSING;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 78650037036     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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