A dataflow control unit for C-to-configurable pipelines compilation flow

Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004

Volumn , Issue , 2004, Pages 332-333

  Cappelli, Andrea ^a   Lodi, Andrea ^a   Mucci, Claudio ^a   Toma, Mario ^a   Campi, Fabio ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DATAFLOW CONTROL; PIPELINED CONFIGURABLE GATE ARRAYS (PICOGA); RECONFIGURABLE LOGIC CELLS (RLC); RECONFIGURABLE PROCESSORS;

ALGORITHMS; CODES (SYMBOLS); COMPUTATIONAL METHODS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; EMBEDDED SYSTEMS; PROGRAM COMPILERS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

PROGRAM PROCESSORS;

EID: 18644384605     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2004.2     Document Type: Conference Paper

References (4)

1. http://www.celoxica.com/technical_library/handel-c/.
2. J. Hauser et al. Garp: A MIPS Processor with a Reconfigurable Coprocessor. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 24-30, 1997.
3. A. Lodi et al. A VLIW Processor with Reconfigurable Instruction Set for Embedded Applications. IEEE Journal of Solid-State Circuits, 38(11):1876-1886, November 2003.
4. C. Mucci et al. A C-based Algorithm Development Flow for a Reconfigurable Processor Architecture. In International Symposium on System-on-Chip, November 2003.