A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture

IPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM

Volumn , Issue , 2008, Pages

  Whitty, Sean ^a   Ernst, Rolf ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; DATA PROCESSING; DISTRIBUTED PARAMETER NETWORKS; DYNAMIC RANDOM ACCESS STORAGE; IMAGE PROCESSING; OPTIMIZATION; TELECOMMUNICATION SYSTEMS;

NETWORK ON CHIPS; PARALLEL AND DISTRIBUTED PROCESSING; RE-CONFIGURABLE ARCHITECTURE;

ARCHITECTURAL DESIGN;

EID: 51049103633     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2008.4536536     Document Type: Conference Paper

References (15)

1. Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, and Abhishek Das. Evaluating the Imagine Stream Architecture. SIGARCH Comput. Archit. News, 32(2):14, 2004.
2. ARM Ltd. PrimeCell MultiPort Memory Controller (PL175). ARM Ltd., 2003.
3. M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, and A. Scandurra. Spidergon: a novel on-chip communication network. In Proceedings of the International Symposium on System-on-Chip, pages 16-18, 2004.
4. Amilcar do Carmo Lucas, Sven Heithecker, and Rolf Ernst. FlexWAFE - A high-end real-time stream processing library for FPGAs. In DAC '07: Proceedings of the 44th annual conference on Design automation, pages 916-921, New York, NY, USA, 2007. ACM Press.
5. Sven Heithecker, Amilcar do Carmo Lucas, and Rolf Ernst. A Mixed QoS SDRAM Controller for FPGA-Based High-End Image Processing. In Workshop on Signal Processing Systems Design and Implementation, page TP.11. IEEE, 2003.
6. Sven Heithecker and Rolf Ernst. Traffic Shaping for an FPGA-Based SDRAM Controller with Complex QoS Requirements. In Design Automation Conference (DAC), pages 575-578. ACM, June 2005.
7. JEDEC. Double Data Rate (DDR) SDRAM Specification. JEDEC Solid State Technology Association, jesd79c edition, March 2003.
8. Brucek Khailany, William J. Dally, and Scott Rixner. Imagine: Media Processing with Streams. IEEE Micro, pages 35-46, March/April 2001.
9. Jeroen A. J. Leitjen, Jef L. van Meerbergen, and Adwin H. Timmer. PROPHID: a Heterogeneous Multi-Processor Architecture for Multimedia. In International Conference on Computer Design, pages 164-169, October 1997.
10. Micron Technology, Inc. 512Mb DDR SDRAM Component: MT46V64M8BN-5B. Data sheet, Micron Technology, Inc., April 2004.
11. Prabhat Mishra, Peter Grun, and Nikil D. Dutt. Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. In 14th International Conference on VLSI Design (VLISD01), pages 70-75. IEEE, Jan 2001.
12. Scott Rixner,William J. Dally, and Ujval J. Kapasi. Memory Access Scheduling. In International Symposium on Computer Architecture, pages 128-138, 2000.
13. Sonics Inc. Sonics MemMax 2.0 Multi-threaded DRAM Access Scheduler. Data sheet, Sonics Inc., 2005.
14. F. Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, and Jürgen Becker. MORPHEUS: Heterogeneous Reconfigurable Computing. In Proceedings of 17th International Conference on Field Programmable Logic and Applications (FPL07), August 2007.
15. Thomson Grass Valley. Homepage. http://www.thomsongrassvalley.com, 2007.