Low-cost concurrent error detection for floating-point unit (FPU) controllers

IEEE Transactions on Computers

Volumn 62, Issue 7, 2013, Pages 1376-1388

  Maniatakos, Michail ^a   Kudva, Prabhakar ^b   Fleischer, Bruce M ^b   Makris, Yiorgos ^c  

^a NEW YORK UNIVERSITY ABU DHABI   (United Arab Emirates)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c The University of Texas at Dallas   (United States)

Author keywords

control logic; Error correction; floating point; IEEE 754

Indexed keywords

ANCILLARY BENEFITS; CLASSICAL APPROACH; CONCURRENT ERROR DETECTION; CONTROL LOGIC; FLOATING POINT UNITS; FLOATING POINTS; IEEE-754; TRANSIENT ERRORS;

ERROR CORRECTION;

DIGITAL ARITHMETIC;

EID: 84878419277     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2012.81     Document Type: Article

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