Reduced precision checking for a floating point adder

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2009, Pages 145-152

  Eibl, Patrick J ^a   Cook, Andrew D ^a   Sorin, Daniel J ^a  

^a Duke University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; ERROR BOUND; ERROR-DETECTION TECHNIQUES; FAULT INJECTION; FLOATING-POINT ADDER; REDUCED PRECISION;

DEFECTS; DIGITAL ARITHMETIC; ERROR DETECTION; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; PROBABILITY DENSITY FUNCTION; SOFTWARE TESTING;

QUALITY ASSURANCE;

EID: 77649294316     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2009.22     Document Type: Conference Paper

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