LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 285-296

  Udipi, Aniruddha N ^a   Muralimanohar, Naveen ^b   Balsubramonian, Rajeev ^a   Davis, Al ^a   Jouppi, Norman P ^b  

^a UNIVERSITY OF UTAH   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS LOCALITY; CHECKSUM; CIRCUIT COMPLEXITY; CORRECTION CODES; DATA MAPPINGS; DATA MEMORY; DRAM DEVICES; ENERGY EFFICIENT; FAULT TOLERANCE MECHANISMS; MEMORY ACCESS; MEMORY CONTROLLER; MEMORY PROTECTION; MEMORY SYSTEMS; MULTI-TIERED; NOVEL CONCEPT; PARITY CODES; PROTECTION SCHEMES; RELIABILITY GUARANTEE; SYSTEM FIRMWARE;

COMPUTER ARCHITECTURE; ENERGY UTILIZATION; FAULT TOLERANCE; FIRMWARE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84864832751     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237025     Document Type: Conference Paper

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