A resilient architecture for low latency communication in shared-L1 processor clusters

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 887-892

  Kakoee, Mohammad Reza ^a   Loi, Igor ^a   Benini, Luca ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CLOSED LOOP CONTROL SYSTEMS; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); NETWORK ARCHITECTURE; TREES (MATHEMATICS);

DATA MEMORY; LOW-LATENCY COMMUNICATION; MESH OF TREES; PROCESS VARIATION; PROCESSOR CLUSTER; SINGLE CYCLE; TIGHTLY-COUPLED; TOLERANT ARCHITECTURES;

MEMORY ARCHITECTURE;

EID: 84862091782     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176623     Document Type: Conference Paper

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