A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 150-151

  Xu, Hui ^a   Tanabe, Jun ^a   Usui, Hiroyuki ^a   Hosoda, Soichiro ^a   Sano, Toru ^a   Yamamoto, Kazumasa ^a   Kodaka, Takeshi ^a   Nonogaki, Nobuhiro ^a   Ozaki, Nau ^a   Miyamori, Takashi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DYNAMICALLY RECONFIGURABLE PROCESSORS; HARDWARE ACCELERATORS; HIGH SCALABILITIES; L2 CACHE; LOW POWER; LOW-POWER CONSUMPTION; MANY-CORE; MULTIMEDIA APPLICATIONS; NETWORK ON CHIP; PROCESSOR CORES; SUPER RESOLUTION; TREE-BASED;

CMOS INTEGRATED CIRCUITS; FIRMWARE; FORESTRY; IMAGE PROCESSING;

VLSI CIRCUITS;

ELECTRIC CIRCUITS; FORESTRY; IMAGE ANALYSIS;

EID: 84866601496     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243834     Document Type: Conference Paper

References (6)

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6. T. Mori, et al., "A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications," JSSCC, 2009, pp. 2957-2965.