Electrical and reliability investigation of Cu TSVs with low-temperature Cu/Sn and BCB hybrid bond scheme

IEEE Electron Device Letters

Volumn 34, Issue 1, 2013, Pages 102-104

  Chang, Yao Jen ^a   Ko, Cheng Ta ^a,b   Chen, Kuan Neng ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

3 D integration; Hybrid bonding; through silicon via (TSV)

Indexed keywords

3-D INTEGRATION; DAISY-CHAIN RESISTANCE; ELECTRICAL CHARACTERIZATION; HYBRID BONDING; KELVIN RESISTANCE; LOW TEMPERATURES; RELIABILITY ASSESSMENTS; RELIABILITY INVESTIGATIONS; RELIABILITY TEST; TEST STRUCTURE; THROUGH SILICON VIAS; THROUGH-SILICON VIA (TSV); WAFER LEVEL;

ELECTRONICS PACKAGING; INTEGRATION; RELIABILITY ANALYSIS;

WAFER BONDING;

EID: 84871803787     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2012.2225136     Document Type: Article

References (12)

1. S. Koester, A. Young, R. Yu, S. Purushothaman, K. N. Chen, D. La Tulipe, N. Rana, L. Shi, M. Wordeman, and E. Sprogis, "Waferlevel 3D integration technology, " IBM J. Res. Develop., vol. 52, no. 6, pp. 583-597, Nov. 2008.
2. A. Topol, D. C. L. Tulipe, L. Shi, D. Frank, K. Bernstein, S. Steen, A. Kumar, G. Singco, A. Young, and K. Guarini, "Three-dimensional integrated circuits, " IBM J. Res. Develop., vol. 50, no. 4. 5, pp. 491-506, Jul. 2006. (Pubitemid 44364166)
3. C. T. Ko and K. N. Chen, "Wafer-level bonding/stacking technology for 3D integration, " Microelectron. Reliab., vol. 50, no. 4, pp. 481-488, Apr. 2010.
4. J. Q. Lu, "3-D hyperintegration and packaging technologies for micro-nano systems, " Proc. IEEE, vol. 97, no. 1, pp. 18-30, Jan. 2009.
5. R. S. Patti, "Three-dimensional integrated circuits and the future of system-on-chip designs, " Proc. IEEE, vol. 94, no. 6, pp. 1214-1224, Jun. 2006. (Pubitemid 46444967)
6. K. N. Chen, S. H. Lee, P. S. Andry, C. K. Tsang, A. W. Topol, Y. M. Lin, J. Q. Lu, A. M. Young, M. Ieong, and W. Haensch, "Structure, design and process control for Cu bonded interconnects in 3D integrated circuits, " in Proc. IEDM, San Francisco, CA, Dec. 2006, pp. 367-370.
7. T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koyanagi, "New threedimensional integration technology using self-assembly technique, " in IEDM Tech. Dig., San Francisco, CA, Dec. 2005, pp. 348-351. (Pubitemid 46370861)
8. F. Liu, R. Yu, A. Young, J. Doyle, X. Wang, L. Shi, K. N. Chen, X. Li, D. Dipaola, and D. Brown, "A 300-mm wafer-level threedimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding, " in Proc. IEDM, San Francisco, CA, Dec. 2008, pp. 1-4.
9. R. Yu, F. Liu, R. Polastre, K. N. Chen, X. Liu, L. Shi, E. Perfecto, N. Klymko, M. Chace, and T. Shaw, "Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding, " in VLSI Symp. Technol., San Francisco, CA, Dec. 2009, pp. 170-171.
10. J. McMahon, E. Chan, S. Lee, R. Gutmann, and J. Q. Lu, "Bonding interfaces in wafer-level metal/adhesive bonded 3D integration, " in Proc. 58th ECTC, Lake Buena Vista, FL, Jun. 2008, pp. 871-878.
11. C. K. Lee, T. Chang, Y. Huang, H. Fu, J. H. Huang, Z. Hsiao, J. H. Lau, C. T. Ko, R. Cheng, and K. Kao, "Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration, " in Proc. 61th ECTC, Lake Buena Vista, FL, Jun. 2011, pp. 1468-1474.
12. P. Benkart, A. Munding, A. Kaiser, E. Kohn, A. Heittmann, H. Huebner, and U. Ramacher, "Three-dimensional integration scheme with a thermal budget below 300C, " Sens. Actuators A, Phys., vol. 139, no. 1/2, pp. 350-355, Sep. 2007. (Pubitemid 47314217)