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Volumn 139, Issue 1-2 SPEC. ISS., 2007, Pages 350-355
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Three-dimensional integration scheme with a thermal budget below 300 °C
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Author keywords
3D stacking; Chip stack; Microsystems; Silicon fabrication technology; Through chip via; Vertical integration
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
EMBEDDED SYSTEMS;
LARGE SCALE SYSTEMS;
MICROPROCESSOR CHIPS;
MICROSYSTEMS;
INTERCONNECT DENSITY;
MEMORY CIRCUITS;
SILICON FABRICATION TECHNOLOGY;
THREE DIMENSIONAL INTEGRATION;
VERTICAL INTEGRATION;
ELECTRIC WIRING;
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EID: 34548179405
PISSN: 09244247
EISSN: None
Source Type: Journal
DOI: 10.1016/j.sna.2007.04.032 Document Type: Article |
Times cited : (20)
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References (9)
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