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Volumn , Issue , 2011, Pages

Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK PERIOD; DETECTION WINDOWS; ERROR-DETECTION SEQUENTIAL; SOURCE COUPLED LOGIC; SUBTHRESHOLD; SUBTHRESHOLD SCL; SYSTEM LEVELS; SYSTEM-LEVEL REQUIREMENTS; TIMING ERROR DETECTION; TIMING MARGIN;

EID: 84856861013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NORCHP.2011.6126746     Document Type: Conference Paper
Times cited : (3)

References (12)
  • 1
    • 78650879825 scopus 로고    scopus 로고
    • A power-efficient 32 bit arm processor using timing-error detection and correction for transient-error tolerance and adaptation to pvt variation
    • D. Bull, S. Das, K. Shivashankar, G. S. Dasika, K. Flautner, and D. Blaauw, "A power-efficient 32 bit arm processor using timing-error detection and correction for transient-error tolerance and adaptation to pvt variation," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 18-31, 2011.
    • (2011) IEEE J. Solid-State Circuits , vol.46 , Issue.1 , pp. 18-31
    • Bull, D.1    Das, S.2    Shivashankar, K.3    Dasika, G.S.4    Flautner, K.5    Blaauw, D.6
  • 4
    • 77949573723 scopus 로고    scopus 로고
    • Measurement of a timing error detection latch capable of sub-threshold operation
    • M. Turnquist and L. Koskinen, "Measurement of a timing error detection latch capable of sub-threshold operation," NORCHIP, 2009.
    • (2009) NORCHIP
    • Turnquist, M.1    Koskinen, L.2
  • 6
    • 67349188103 scopus 로고    scopus 로고
    • Leakage current reduction using subthreshold source-coupled logic
    • A. Tajalli and Y. Leblebici, "Leakage current reduction using subthreshold source-coupled logic," IEEE Trans. Circuits Syst. II, vol. 56, no. 5, pp. 374-378, 2009.
    • (2009) IEEE Trans. Circuits Syst. II , vol.56 , Issue.5 , pp. 374-378
    • Tajalli, A.1    Leblebici, Y.2
  • 9
    • 46749108096 scopus 로고    scopus 로고
    • Subthreshold source-coupled logic circuits for ultra-low-power applications
    • A. Tajalli, E. J. Brauer, Y. Leblebici, and E. Vittoz, "Subthreshold source-coupled logic circuits for ultra-low-power applications," IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1699-1710, 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.7 , pp. 1699-1710
    • Tajalli, A.1    Brauer, E.J.2    Leblebici, Y.3    Vittoz, E.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.