Analysis and design of ultra-low power subthreshold MCML gates

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 2557-2560

  Alioto, Massimo ^a   Leblebici, Yusuf ^b  

^a UNIVERSITY OF SIENA   (Italy)

^b EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS AND DESIGN; CMOS TECHNOLOGY; DC CHARACTERISTICS; MONTE CARLO SIMULATION; MOS CURRENT-MODE LOGIC; POWER CONSUMPTION; POWER VARIATIONS; PROCESS VARIATION; SUBTHRESHOLD; SUBTHRESHOLD CMOS; THEORETICAL RESULT; TYPICAL VALUES; ULTRA-LOW POWER;

CMOS INTEGRATED CIRCUITS; MONTE CARLO METHODS;

COMPUTER SIMULATION;

EID: 70350180857     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5118323     Document Type: Conference Paper

References (10)

1. A. Wang, B. H. Calhoun, A. P. Chandrakasan, Sub-Threshold Design for Ultra Low-Power Systems, Springer, 2006.
2. S. Hanson, B. Zhai, D. Blaauw, D. Sylvester, A. Bryant, and X. Wang, "Energy optimality and variability in subthreshold design," in Proc. of ISLPED 2006, pp. 363-365, 2006.
3. M. Orshanky, S. Nassif, D. Boning, Design for Manufacturability and Statistical Design - A Constructive Approach, Springer, 2008.
4. A. Tajalli, E. J. Brauer, Y. Leblebici, E. Vittoz, "Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications," IEEE J. of Solid-State Circuits, vol. 43, no. 7, July 2008.
5. M. Alioto, Y. Leblebici "Circuit techniques to reduce the supply voltage limit of subthreshold MCML circuits," in Proc. of VLSI-SoC 2008, pp. 239-244, Rhodes Island (Greece), Oct. 2008.
6. F. Cannillo, C. Toumazou, and T. S. Lande, "Bulk-drain connected load for subthreshold MOS current-mode logic," IEE Electron. Lett., vol. 43, no. 12, pp. 662-664, Jun. 2007.
7. A. Tajalli, F. K. Gurkaynak, Y. Leblebici, M. Alioto, E. J. Brauer, "Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage," in Proc. of ISCAS 2008, USA, May 2008.
8. M. Alioto, G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits), New York, Springer, 2005.
9. M. Alioto, and G. Palumbo, "Design strategies for source coupled logic gates," IEEE Trans. on Circuits and Systems - part I, vol. 50, no. 5, pp. 640-654, May 2003.
10. M. Alioto, G. Palumbo, M. Pennisi, "Analysis of the impact of process variations on static logic circuits versus fan-in," in Proc. of ICECS 2008, pp. 137-140, Malta, Aug. 2008.