Leakage current reduction using subthreshold source-coupled logic

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 56, Issue 5, 2009, Pages 374-378

  Tajalli, Armin ^a   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

Author keywords

CMOS digital circuits; Leakage; Source coupled logic (SCL); Subthreshold CMOS; Subthreshold SCL (STSCL)

Indexed keywords

CMOS INTEGRATED CIRCUITS; COUPLED CIRCUITS; DELAY CIRCUITS; ELECTRIC POWER UTILIZATION; EMITTER COUPLED LOGIC CIRCUITS; LEAKAGE (FLUID); LEAKAGE CURRENTS; LOW POWER ELECTRONICS; SENSITIVITY ANALYSIS; TOPOLOGY;

CMOS DIGITAL CIRCUITS; LEAKAGE CURRENT REDUCTION; NANOMETER-SCALE TECHNOLOGIES; SOURCE COUPLED LOGIC; SUB-THRESHOLD LEAKAGE CURRENTS; SUBTHRESHOLD CMOS; SUBTHRESHOLD SCL (STSCL); ULTRALOW POWER APPLICATION;

COMPUTER CIRCUITS;

EID: 67349188103     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2009.2019167     Document Type: Article

References (8)

1. M. Pedram and J. Rabaey, Power Aware Design Methodologies. Norwell, MA: Kluwer, 2002.
2. M. Anis and M. Elmasry, Multi-Threshold CMOS Digital Circuits, Managing Leakage Power. Norwell, MA: Kluwer, 2003.
3. H. Soeleman, K. Roy, and B. C. Paul, "Robust subthreshold logic for ultra-low power operation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 1, pp. 90-99, Feb. 2001.
4. B. H. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, Sep. 2005.
5. N. Verma, J. Kwong, and A. Chandrakasan, "Nanometer MOSFET variation in minimum energy subthreshold circuits," IEEE Trans. Electron Devices vol. 55, no. 1, pp. 163-174, Jan. 2008.
6. A. Tajalli, E. Vittoz, Y. Leblebici, and E. J. Brauer, "Ultra-low power subthreshold current-mode logic ulitising PMOS load device concept," Electron. Lett., vol. 43, no. 17, pp. 911-913, Aug. 2007.
7. A. Tajalli, E. J. Brauer, Y. Leblebici, and E. Vittoz, "Subthreshold source-coupled logic circuits for ultra-low power applications," IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1699-1710, Jul. 2008.
8. C. C. Enz and E. A. Vittoz, Charge-Based MOS Transistor Modeling. Hoboken, NJ: Wiley, 2006.