Logic masking for SET Mitigation Using Approximate Logic Circuits

Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012

Volumn , Issue , 2012, Pages 176-181

  Sanchez Clemente, A ^a   Entrena, L ^a   Garcia Valderas, M ^a   Lopez Ongil, C ^a  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

Author keywords

Approximate circuit; Error detection and correction; Single Event Transient; Soft error; testability

Indexed keywords

CONVENTIONAL TECHNIQUES; ERROR COVERAGE; ERROR DETECTION AND CORRECTION; FAULT COVERAGES; HARDWARE REDUNDANCY; OPTIMAL BALANCE; SINGLE EVENT TRANSIENTS; SOFT ERROR; TESTABILITY;

LOGIC CIRCUITS;

TRANSIENTS;

EID: 84869152191     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2012.6313868     Document Type: Conference Paper

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